Wei Wu, Vice-Chair of RISC-V International P Extension Task Group
PLCT Lab, ISCAS.
By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency.
The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.
Kazutoshi Wakabayashi, Senior Manager
Embedded Systems Solution Division, NEC
OVP is widely used by our customers, who demanded the integration with CyberWorkBench. This integration significantly broadens CWB's HW/SW co-verification support. We were also very impressed with Imperas technical support helping us achieve this integration extremely quickly and efficiently.