By integrating our Xcelium Logic Simulator with Imperas's RISC-V verification technology, we've empowered NSITEXE to design the next-generation of its Akaria processors, which are optimized for safety-critical applications and compliant with the ISO 26262 ASIL D standard.
Our work together exemplifies Cadence’s commitment to collaboration and innovation to support our customers in the rapidly evolving semiconductor industry.
Philippe Berger, CEO
Dolphin Design
Our verification methodology for the Panther DSP/AI Accelerator IP needs to address not just the full range of the current configuration options but also the roadmap for Panther.
ImperasDV is the cornerstone of our simulation-based DV strategy, with the Imperas golden reference model, scoreboard, verification IP, functional coverage analysis and debug efficiency.