At Ventana, our teams of developers are building the foundational processor IP and chiplet building blocks that will enable a step change in performance for the most demanding compute workload markets.
Our verification strategy is to exercise the RISC-V based processors across the most demanding scenarios and are using Imperas RISC-V vector test suites in addition to the Imperas golden reference model in our verification environment.
Yunsup Lee, co-founder and CTO
SiFive
SiFive’s Core Designer allows our customers to customize our broad portfolio of RISC-V Core IP for their particular application. The donation of a robust, commercial-quality simulator such as riscvOVPsim™ will enable them to adopt RISC-V even faster. This is the level of close industry collaboration that will drive the successful adoption of RISC-V.