At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors.
As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.
Sandeep Vij, President and CEO
MIPS Technologies
We chose Imperas and the Open Virtual Platform technology because of the quality of the models and technology. We see the positive momentum and leadership position of OVP, and believe this is the best technology for instruction accurate simulation of processor core models.