The open RISC-V ISA specification is an excellent starting point and open-source processor IP cores, such as the CORE-V family, have real potential to change the industry.
The high-quality open-source CORE-V CV32E40P core now allows the broadest participation in the RISC-V revolution, the OpenHW MCU Dev/Kit project is just one example of the innovations that can now be developed from the quality foundation provided by the CV32E40P core, having been verified with the CORE-V-VERIF testbench which leverages the Imperas RISC-V golden reference model.
Professor Fernando Gehm Moraes
Pontifical Catholic University of Rio Grande do Sul, Brazil - PUCRS
At PUCRS, we use Imperas virtual platforms in projects on multiprocessor SoC modeling, power evaluation, and programmability, as well as computer science graduate program courses on SoCs and research architecture. Our research group (Grupo de Apoio ao Projeto de Hardware, or Hardware Design Support Group), also leverages these tools.