Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Imperas Golden RISC-V Reference Model helped us find many bugs in our cores.
However, the RISC-V architectural tests yielded no bugs, which is expected since the architectural tests are a subset of full verification.
Manuel Andreu, Team Lead for Software Development
Solectrix GmbH
We were able to easily merge the Imperas simulator into our automated workflow on our build server for both unit and integration testing. Running our tests with the production binaries on the simulator enabled us to find bugs that were not found when the software was cross compiled to the x86 Windows environment.