Silicon Labs selected Imperas simulation tools and RISC-V models for our design verification (DV) flow because of the quality of the models and the ease of use of the Imperas environment.
The Imperas golden reference model of the RISC-V core and their experience with processor RTL DV flows were also critical to our decision.
Krishna Raghavan, President
MIPS IP Licensing, Wave Computing
The Imperas simulation and modeling technology has been a reliable and high-quality testing model used internally by the MIPS engineering team for many years. We are delighted to partner with Imperas to make this industrial-grade simulation technology available to support the MIPS Open program and further the momentum around open hardware development.