The open ISA of RISC-V is enabling a new wave of processor design innovation across the spectrum of compute requirements in almost all market segments.
High quality processor verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV enables the eSOL TRINITY team to support the expert design teams at NSITEXE and other leading adopters of RISC-V in Japan.
Mike Ingster, President and Founder
Quantum Leap Sales
Imperas solutions for early software development have never been more appropriate with development schedules more critical than ever. We believe that simulation-based verification is fast becoming an essential requirement in complex SoCs, and together with advanced debug and analysis tools for many-core and heterogeneous designs will greatly reduce development schedules for next generation devices.