SoC projects are all about partnerships; hardware and software engineers working together, with a complete ecosystem of supporters.
With this Imperas collaboration, our mutual customers will benefit from the availability of SiFive qualified models that are compatible with the mainstream EDA tool flows.
Dr. Charlie Su, President and CTO
Andes Technology Corp.
RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.
The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.