New memory approaches and challenges in scaling CMOS point to radical changes — and potentially huge improvements — in semiconductor designs.

We take many things in the semiconductor world for granted, but what if some of the decisions made decades ago are no longer viable or optimal? We saw a small example with finFETs, where the planar transistor would no longer scale. Today we are facing several bigger disruptions that…

Whether EDA is doing enough to help develop and drive new methodologies remains a subject of debate.

Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification…

Is the tools market really changing, or has this always been the case?

More companies appear to be creating custom EDA tools, but it is not clear if this trend is accelerating and what it means for the mainstream EDA industry.

Whenever there is change, there is opportunity. Change can come from new abstractions, new options for optimization, or new limitations that are imposed on a tool or flow. For example, the slowing of Moore’…

The industry is evolving, with new players, new problems, and new challenges. Is this why verification appears to be struggling?

Semiconductor Engineering sat down to discuss differences between hardware and software verification and changes and challenges facing the chip industry, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification…

As if Intel testing the RISC-V waters wasn’t news in itself, the semiconductor behemoth’s Intel Pathfinder for RISC-V initiative is now making the headlines. RISC-V is an open standard instruction set architecture (ISA) that offers chip developers the freedom to configure a custom processor with standard extensions and configuration options.
Vijay Krishnan, general manager of RISC-V Ventures at Intel, acknowledges that the adoption of RISC-V is at an inflection point across…

Aspiring to become a facilitator in the open [standard] RISC-V community, Intel is decidedly humble in its approach to enabling SoC designers who use RISC-V cores.

For the world’s largest CPU vendor to become a genuine facilitator for the open [standard] RISC-V community, Intel must demonstrate its intent and commitment. Is its Pathfinder initiative for RISC-V enough? Can Intel gain the trust from those in the RISC-V…

No more not-invented here for the chip giant when it comes to processor architectures.

Much like IBM after the PC architecture ran away from it and almost collapsed Big Blue’s highly profitable minicomputer and mainframe businesses, Intel has been through some soul-searching in the wake of Arm’s expansion from the world of cellular phones into just about everything else. 
Intel has moved from a company that sued relentlessly to try to maintain…

The functional verification task keeps growing. How well is the industry responding to growing and changing demands?

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW…

The September 8 learning event from Electronic Design will feature in-depth coverage of RISC-V architecture, hardware, software, and a robust panel discussion.

The open [standard] RISC-V instruction set architecture (ISA) has taken the development community by storm as more companies have implemented chips based on RISC-V. The architecture is…