RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.
The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.
Duncan Graham
University Program Manager, Imperas Software
The Imperas University Program encourages participation in the embedded systems community in three ways: use on research projects, use in the classroom, and sharing of virtual platform models through the Open Virtual Platforms (OVP) Library.