Imperas and Industry Articles

Accelerating OS Bring-up And Software Debug across the Spectrum of Electronics Systems

Embedded Systems Engineering EECatalog

As software complexity is increasing exponentially, companies must adopt better ways to address problems, as eventually the existing methods will no longer be sufficient. And, one serious failure changes everything for your business and your career. One lesson to be learned from SoC design and verification:  A structured methodology makes execution predictable and reduces risk, benefits that argue for a more formalized approach within the embedded software development domain.

In the October issue of Embedded Systems Engineering, Imperas CEO, Simon Davidmann discusses the issues in porting operating systems to new SoC and hardware platforms and uses the case study of porting Linux to an Altera platform.

To read the article, click here.

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Simon Davidmann: A re-energized Imperas Tutorial at DAC 2017

Peggy Aycinena (freelance journalist and Editor of EDA Confidential at www.aycinena.cominterviewed Simon Davidmann (Imperas CEO) on EDACafe about the recent Imperas Tutorial at DAC 2017 on Virtual Platform Based Linux Bring Up Methodology. Peggy Aycinena.

The discussion was wide-ranging and they also covered IP, operating systems, embedded / hardware-dependent software, and more.

To read the interview on EDACafe, please visit: Link to EDACafe.

For slides from the DAC tutorial, see: http://www.imperas.com/tutorial-from-dac-2017-virtual-platform-based-linux-bring-up-methodology

Five Minutes With... - Embedded Computing Design - Larry Lapides

Five Minutes With… Larry Lapides, vice president, Imperas

The best CPU architecture in the world won’t do you much good if the ecosystem falls flat.

RISC-V, the new kid on the block when it comes to instruction-set architectures (ISAs), is up against that stumbling block right now - it needs tools to not just survive, but to thrive.

In this week's Five Minutes with…discussion, Rich Nass of Embedded Computing Design and Larry Lapides, VP of Imperas talked about the present and future of the RISC-V ecosystem  ... click here to read more and listen to the audio interview.

Click here to go directly to the interview on YouTube.

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Bulls, Bears and Bunnies: The 6th RISC-V Workshop in Shanghai

embedded computing design

The 6th RISC-V Workshop was held May 8-11 in Shanghai.   RISC-V is, of course, the open-source processor architecture invented and introduced by the University of California, Berkeley in 2014. The previous workshop, held last November in Silicon Valley, attracted around 350 participants; this workshop about the same.

The opening statement of the Imperas presentation at the workshop was "The size of the RISC-V market share will depend more on the software ecosystem than on specifics of RISC-V implementations."  The meat of the presentation focused on modern embedded software development methodology, specifically on Continuous Integration Continuous Test (CI / CT) subset of the Agile methodology.

To read the article, click here.

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Use a virtual platform to maintain security

embedded computing design

One of the big challenges in the deployment of IoT across varied markets is security. This is a big challenge for both hardware and software and there needs to be a pragmatic approach for developers.

The use of Hypervisors is becoming increasingly common - and Larry Lapides of Imperas has written about the use of Virtual Platforms with Hypervisors.

To read the article, click here.

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Silicon Without Software is Just Sand - EE Journal - Amelia Dalton

Embedded Software Development with Virtual Platforms

Shifting Left with Imperas

No one builds a chip without simulation, right? In this week’s Fish Fry, Amelia Dalton of Electronic Engineering Journal takes a closer look at the value of virtual prototypes to simulate embedded software. Simon Davidmann (CEO - Imperas) and Amelia chat about about why Simon thinks no one should design embedded software without simulation, and the benefits of using virtual platforms to develop a verification and test environment.

 

Follow the link to listen to the interview / Fish Fry....

[Amelia's Fish Fry's are one-on-one audio interviews  / podcasts with industry experts / executives about topical issues and technologies.]

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Automating System Design

The impact of the chip’s changing role in the system is becoming clearer.

Ann Steffora Mutschler of Semiconductor Engineering has written an interesting article on System Level design and its automation.

There are comments from Wally Rhines (chairman & CEO of Mentor), Simon Davidmann (president & CEO Imperas), Nandan Nayampally (VP marketing ARM), Nimish Modi (snr VP Cadence) and John Koeter (VP Synopsys).

Change is underway in the chip design world, creating opportunities and challenges that reach far beyond questions about whether Moore’s Law is slowing or stopping.

Never before in the history of semiconductors has design been so complex and sophisticated, and never has it touched so many lives in so many interesting ways. This is...

To read the article, click here.

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ESL Flow Is Dead

Brian Bailey of Semiconductor Engineering recently chaired a panel at DVCon on ESL.

Expecting the future to replicate the past always leads to surprises and when it comes to migration of abstraction for semiconductor design, the future remains unclear.

Brian interviewed several industry leaders with experience in the field and provides interesting insights into why ESL took a long time to get where it has...

Simon Davidmann, CEO of Imperas was quoted several times. For example Simon said: “Everyone is trying to do more with RTL, more design, more verification, more complexity, and they needed a better solution. The industry came up with a C++ class language (SystemC) and then tried to look at what they could do with it. What is needed is to move away from the EDA vendors trying to define ways to sell the technologies they have, to asking the question, ‘How are we going to design systems which are incredibly complex, containing many processors, many hardware blocks and more software than you can imagine?’ How can we design things in a better way? How do we verify things in a better way?”...

To read the article, click here.

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System-Level Verification Tackles New Role

Brian Bailey of Semiconductor Engineering recently got several experts together for a round table discussion entitled:

The role of system-level verification is not the same as block-level verification and requires different ways to think about the problem.

The experts included Larry Lapides of Imperas, and also staff from Cadence, Mentor, and Breker Verification.

The discussion started with reflection on a keynote at DVCon this year that Wally Rhines, chairman and CEO of Mentor Graphics, gave. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem...

Follow the link to read the first episode / article click here.

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Imperas from Today to Tomorrow with Intent

The challenge yesterday, today and tomorrow in technology is for people to move more towards the software and away from a strictly hardware-centric point of view

Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com. In December Peggy interviewed Simon Davidmann, Imperas CEO, on his views for an article on EDACafe.

Simon Davidmann and the Imperas team are based near Oxford in the UK. Nonetheless, Davidmann is a regular at Silicon Valley events throughout the year.

I spoke with Davidmann during one of his recent visits to Northern California. Per usual, the conversation was unscripted and informative; I asked for an update on Imperas, and Davidmann started at 35,000 feet.

“Let’s start with a bigger picture than just the..."

Follow the link to read the full article.

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