Zbyszek Zalewski, General Manager, Hardware Division
Aldec
The integration of HES with OVPsim enables hardware and software design teams to implement virtual models of processors, memory and peripherals while the RTL modules run in the emulator board. This new integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.
Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH Zurich
RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.