Comments
Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon LaboratoriesSimulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.
Nobuyuki Ueyama, President
eSOL TRINITY Co., Ltd.RISC-V is enabling a new wave of design innovation, and successful projects depend on quality processor IP and dependable design platforms that offer architecture exploration and early software development.
Having supported the NSITEXE team on the extensive internal RISC-V processor verification, as well as on the virtual platform development task for multiple projects, the support team at eSOL TRINITY is now able to assist developers as they build the next generation of SoC designs using the Imperas tools and reference models for the NSITEXE Akaria processors.