Virtual platforms enable the essential early development of software well before RTL or silicon prototypes are available, which dramatically accelerates the time to market.
In addition, for the next generation of automotive AI designs, the early architectural exploration of the SoC helps validate the system design and becomes the reference model for RTL verification.
Sebastian Ahmed, Senior Director of R&D
Silicon Labs
Silicon Labs selected Imperas simulation tools and RISC-V models for our design verification (DV) flow because of the quality of the models and the ease of use of the Imperas environment.
The Imperas golden reference model of the RISC-V core and their experience with processor RTL DV flows were also critical to our decision.