Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Golden RISC-V Reference Model was used as the “go/no-go” model to determine the RTL correct behavior with any discrepancies, bugs or issues with the design, tests, specifications, or test bench.
Sebastian Ahmed, Senior Director of R&D
Silicon Labs
Silicon Labs selected Imperas simulation tools and RISC-V models for our design verification (DV) flow because of the quality of the models and the ease of use of the Imperas environment.
The Imperas golden reference model of the RISC-V core and their experience with processor RTL DV flows were also critical to our decision.