RISC-V is ideal for the latest compute requirements of single-core embedded controllers through to multicore arrays for high performance computing applications.
Companies like Imperas are leading the charge in making SoC design and verification flow easier to further accelerate the mass adoption of RISC-V.
Krystian Bacławski, Professor
Institute of Computer Science at University of Wroclaw
OVPsim beats QEMU in fidelity in CPU simulation - its determinism and speed were pretty impressive. OVPsim configurability is a big advantage as well. We were able to configure low-level CPU features, thanks to comprehensive documentation. I was also enthusiastic about the machine description file. It was easy to connect a missing interrupt signal we needed.