Comments
Wei Wu, Vice-Chair of RISC-V International P Extension Task Group
PLCT Lab, ISCAS.By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency.
The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.
John Min, Director, Processor Technology Marketing
Imagination TechnologiesMIPS Warrior CPUs provide industry leading feature sets, performance, area and power consumption. Partnering with Imperas to provide models in their innovative virtual platform tools provides a huge advantage to MIPS users. These models, together with Imperas’ new Extendable Platform Kits (EPKs) that let users run high-speed simulations of MIPS-based SoCs on any suitable PC - can benefit MIPS customers and anyone developing software for MIPS platforms. It is an additional benefit to our users to enable them to use the Codescape debugger for software development on both virtual platforms and hardware platforms.