Jérôme Quévremont, vice-chair of OpenHW Cores Task Group
Thales Research & Technology
Following the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores.
The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.
Hermann Haslauer, Head of Embedded Software Support Engineering
Palfinger Europe GmbH
Palfinger is the global leader for innovative crane and lifting solutions.
As our embedded development teams develop and implement our roadmap for digitalization and artificial intelligence, the need for software quality testing has never been greater. The TESSY tool together with the Imperas virtual platform simulators and OVP models of Arm processors, are a quality combination that we use as a foundation of our software test and maintenance process.