Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon Laboratories
Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.
Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
A key part of the RISC-V privilege specification that is fundamental for OS and application security is the PMP feature.
Enabling its correct operation is essential for security applications, and the Imperas PMP test suites are a valuable contribution to the RISC-V compatibility and verification community.