As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.
Simon Davidmann, Founder & CEO
Imperas Software
We are proud to extend our long-standing relationship with Andes, and now announce Andes certification of our OVP models for their 32-bit/64-bit CPU cores, as a reference simulator.