Jérôme Quévremont, vice-chair of OpenHW Cores Task Group
Thales Research & Technology
Following the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores.
The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.
Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
A key part of the RISC-V privilege specification that is fundamental for OS and application security is the PMP feature.
Enabling its correct operation is essential for security applications, and the Imperas PMP test suites are a valuable contribution to the RISC-V compatibility and verification community.