Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications

Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications

DVCon 2020

Join Andes, Imperas, and UltraSoC on this webinar to learn how to easily optimize (including custom instructions and Vector, DSP extensions), accurately simulate, and precisely instrument, multicore RISC-V designs for AI Inferencing or ML applications.

This webinar will be run twice on 6 May 2020, at 8am PDT (4pm BST, 5pm CET, 11pm CST) and 5pm PDT (1am BST, 2am CET, 8am CST on May 7). Registering will allow you to join at both times. However, it would be helpful if you could indicate which webinar you intend to join when your register your attendance.

Click here to register your free place.

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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