Comments
Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH ZurichRISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.
Hideki Sugimoto, CTO
NSITEXE, Inc., a group company of DENSO CorporationThe NSITEXE Akaria processors, developed with the use of Imperas RISC-V verification technology and the leading-edge SystemVerilog simulator and debug tools from Cadence, are targeted to address the high-performance requirements for AI and automotive requirements. The Akaria processors include the necessary features and quality to achieve the ISO 26262 ASIL D functional safety standard, in addition to being optimized and efficient processors for the next-generation embedded application.
As the NSITEXE Akaria processors are adopted across a wide range of next-generation automotive, safety-critical, and embedded applications, the verification methodology with the support from Imperas and Cadence has been invaluable in achieving our quality goals and on-time development schedule.