The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development.
The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.
G. S. Madhusudan, CEO
InCore
RISC-V momentum and interest is wide-ranging across academic and industry. In providing support for the IIT Madras Shakti processors, InCore sees an increasing attention to test and verification that will be supported with riscvOVPsim.