RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.
The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.
Rick O’Connor, President & CEO
OpenHW Group
The defining goal of the OpenHW group is to deliver high quality open source IP cores, by leveraging the leading verification methodologies compatible with the established EDA commercial SoC design flows.
To support our world class IP portfolio, the OpenHW working groups are enabling adoption with tools and software support for CORE-V processors. The Imperas contribution with the new free ISS, riscvOVPsimCOREV will be the foundation reference to all software tasks.