Melaine Facon, Director of Codasip’s French Design Centre
Codasip
An open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.
With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.
Hideki Sugimoto, CTO
NSITEXE, a group company of DENSO Corporation
For the automotive market our customers expect the highest standards of quality and design assurance. NSITEXE selected the Imperas Vector Extensions Compliance test cases and RISC-V Reference Model as a foundation for our simulation-based design verification (DV) plans.