At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors.
As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.
Miroslav Popovic
Professor, University of Novi Sad, Serbia
Using Imperas and OVP in my course on Real-Time System Programming is an immense benefit. Embedded software development is a growing need worldwide, and advanced methodologies such as Imperas delivers are required for accelerated coding and quality.