Imperas enables eSOL TRINITY to create new value for our customers by reducing time and cost-to-market, while improving their overall system performance. We believe partnership with Imperas will maximize synergy effect of our expertise and knowledge in embedded software development scene in Japan.
Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon Laboratories
Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.