Europractice Cadence and Imperas Virtual Prototyping Information Day, June 18, STFC Rutherford Appleton Laboratory, UK

The Microelectronics Support Centre at STFC Rutherford Appleton Laboratory is holding a free Virtual Prototyping information day with hands-on lab sessions, featuring Cadence VSP, Imperas, and the Xilinx Zynq™ Virtual Platform.  Imperas was recently added to the Europractice vendor list. 

The information day will include technical presentations from Imperas on OVP fast processor models and the Imperas M*SIM simulator, and Cadence on the Virtual System Platform (VSP) tool.  The Cadence virtual platform of the Xilinx Zynq device uses the Imperas OVP model of the dual core ARM Cortex™-A9 with the M*SIM simulator. 
A hands-on Imperas lab will allow attendees to explore the Imperas tools, by building a system using an OVP processor model, and modifying the processor instructions and extending the instruction set. 
This will be followed by a hands-on Cadence VSP lab which will use the Xilinx Zynq Virtual Platform as an example.  The lab will cover running and extending the Xilinx Zynq virtual platform (and this can be extended to any Virtual Platform), and carrying out Hardware and Software co-debug and development using Cadence VSP and the Cadence Incisive tools.