All Imperas News

Five Minutes With... - Embedded Computing Design - Larry Lapides

Five Minutes With… Larry Lapides, vice president, Imperas

The best CPU architecture in the world won’t do you much good if the ecosystem falls flat.

RISC-V, the new kid on the block when it comes to instruction-set architectures (ISAs), is up against that stumbling block right now - it needs tools to not just survive, but to thrive.

In this week's Five Minutes with…discussion, Rich Nass of Embedded Computing Design and Larry Lapides, VP of Imperas talked about the present and future of the RISC-V ecosystem  ... click here to read more and listen to the audio interview.

Click here to go directly to the interview on YouTube.

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Bulls, Bears and Bunnies: The 6th RISC-V Workshop in Shanghai

embedded computing design

The 6th RISC-V Workshop was held May 8-11 in Shanghai.   RISC-V is, of course, the open-source processor architecture invented and introduced by the University of California, Berkeley in 2014. The previous workshop, held last November in Silicon Valley, attracted around 350 participants; this workshop about the same.

The opening statement of the Imperas presentation at the workshop was "The size of the RISC-V market share will depend more on the software ecosystem than on specifics of RISC-V implementations."  The meat of the presentation focused on modern embedded software development methodology, specifically on Continuous Integration Continuous Test (CI / CT) subset of the Agile methodology.

To read the article, click here.

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New Open Virtual Platforms Processor Models for ARM, Imagination Technologies, RISC-V and Renesas Accelerate Software Development

Latest OVP Models and Virtual Prototype Software Release with iGen, Available Now

Oxford, United Kingdom, May 23, 2017 - Imperas Software Ltd., the leader in high-performance software simulation, today announced the availability of new Open Virtual Platforms (OVP) models for ARM, Imagination Technologies, RISC-V and Renesas processors, along with a new OVPsim software release including the iGen modeling tool.

For embedded software and hardware developers, virtual platforms are increasingly important, especially for multi-core designs. These new OVP library models, for ARM’s ARMv8.1 architecture for the Cortex-A family, Imagination Technologies MIPS I6400, Renesas RH850, and RISC-V, extend Imperas’ leadership in virtual prototyping. OVP models, APIs and the OVPsim virtual platform simulator support development and customization of instruction-accurate platforms for SoCs and larger systems for software development, debug and test.

New Imperas Virtual Platform Software Delivers Performance and Models for Automotive, IoT and Security

New Release Doubles Performance, Adds ARM, Imagination Technologies, RISC-V and Renesas Models, Features Virtual Prototype Modeling Tool

Oxford, United Kingdom, May 23, 2017 - Imperas Software Ltd., the leader in high-performance software simulation, today announced a new software release, focused on enhanced solutions across automotive, IoT, security and other markets, and extending Imperas’ leadership in virtual prototyping.

Highlights include:

Imperas Virtual Platform Based Software Tools at DAC 2017

Virtual Prototyping in Demonstrations of Software Development Using Continuous Integration and Jenkins, Debug and Test, and a Tutorial on Linux Bring Up on Heterogeneous Multiprocessor SoCs

Oxford, United Kingdom, May 22, 2017 - Imperas Software Ltd., the leader in high-performance software simulation, today announced their participation at the Design Automation Conference (DAC) 2017, inviting developers of electronic products to register for a demonstration of Imperas virtual platforms for embedded software and systems development, debug and test at the Imperas booth in the World of IoT pavilion, booth #521.

DEMO HIGHLIGHTS: See Imperas virtual platform-based solutions for embedded software development, debug, analysis, and verification demos in the World of IoT pavilion, booth #521.

Design Automation Conference: Linux Tutorial, Demos, June 2017

At the Design Automation Conference (DAC), June 18-22 in Austin, Texas, Imperas will present a tutorial on Linux Bring Up on Heterogeneous Multicore SoCs, and will exhibit and show demos in the IoT area of the DAC exhibit floor.

More information to come soon.

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RISC-V Gains a Software Development Solution from Imperas

Imperas Joins RISC-V Foundation: Virtual Platforms and Models Now Available, Demonstrations at the 6th RISC-V Workshop in Shanghai, China and the 2017 Design Automation Conference

Oxford, United Kingdom, April 27, 2017 - Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their membership in the RISC-V Foundation, along with Imperas virtual platform and model support for the RISC-V architecture, available now. Imperas will demonstrate these embedded software development solutions at the 6th RISC-V Workshop in Shanghai, China May 8-11, 2017 and also at the Design Automation Conference (DAC) 2017 in Austin, Texas June 18-22, 2017.

The RISC-V Foundation drives the adoption of the new RISC-V instruction set architecture (ISA), set to become a standard open architecture for industry implementations, and directs its future development. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Imperas Presents, Demos at the Agile for Embedded Conference, May 2017

Imperas is sponsoring the Agile for Embedded Conference May 3, 2017 at Easthampstead Park, Berkshire, UK and will be demonstrating the Imperas tools.

Also, Imperas is presenting a technical paper on “Target-Based Simulation for Testing of Embedded Software in CI Flows” by Lee Moore, Duncan Graham, Simon Davidmann, and Larry Lapides of Imperas Software.

For more information, please read the press information at the link here. 

We hope to see you there.

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