Archive for August, 2010

Imperas presents OVP Fast TLM Models at European SystemC User Group Meeting

Friday, August 27th, 2010

Title: Open Virtual Platforms tools working with a SystemC/TLM2.0 virtual platform for embedded software development

When/Where : Tuesday, September 14th, 2010 at Southampton University, UK

Imperas CEO, and OVP Founding Director, Simon Davidmann presents at the Fall 2010 European SystemC User’s Group Meeting as part of the Forum on Design Languages on Tuesday, September 14th, 2010 at Southampton University, UK.

The talk will discuss the latest advances in Fast CPU modeling using the latest OVP release and how speeds of over 2,000 mips of instruction accurate simulation can easily be achieved and how this performance enables efficient embedded software development.

Full agenda and more informaton can be found: http://www.ti.uni-tuebingen.de/escug

It is expected that the slides of the talk will be made available from that site - if you cannot find them - please email us - info@imperas.com

OCP-IP Provides Virtual Platform Leveraging OVP Fast ARM Models

Tuesday, August 24th, 2010

Uses OVP ARM Integrator platform, OVP ARM processor models and OCP-IP SystemC TLM Modeling kit

Open Core Protocol International Partnership (OCP-IP), the organization delivering a common standard for intellectual property core interfaces that facilitate “plug and play” SoC design, and CircuitSutra, experts in SystemC modeling and embedded software development, along with Imperas, the company providing the infrastructure for the future of software virtual platforms and enabling the next generation of embedded software development, today announced the availability of a Virtual Platform Demo created utilizing OCP-IP’s advanced Modeling Kit. This example platform acts as a guide to OCP-IP members enabling them to quick-start their ESL activities using the OCP-IP TLM Modeling Kit; which is fully compatible with OSCI’s TLM 2.0.1. Both the kit and Virtual Platform examples are free to both OCP-IP members and non-members.

The Virtual Platform Demo utilizes Open Virtual Platforms (OVP) technology…

For more information, please read the full press release here, or download it here.

You can get the virtual platform here, and see the OVP information here and here.

For the CircuitSutra presentation on the virtual platform visit here.

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Faster Than Reality - Whatever it is, whatever it does, it’s all good as long as it’s fast.

Monday, August 16th, 2010

An interesting article in the Embedded Technology Journal by Bryon Moyer

It better be fast.

Whatever it is, whatever it does, it’s all good as long as it’s fast.

We live for speed in our supercharged world.

Software simulation is not really new; instruction-set simulators (ISSs) have been around forever. But we’ve gone from cross-development between platforms to building software for traditional (meaning PC-board-based) embedded systems to development of software for single-chip embedded systems.

The costs of getting it wrong when developing across desktop platforms are in time and annoyance. Similarly with traditional embedded systems; you might have to do a PC-board spin, but, while not desirable, it’s not a deal-killer.

Maybe I’ve been asleep for a while as the world passed me by, but something slapped me upside the head a couple weeks ago at DAC when talking with Imperas. They have just announced that their software simulation speed has improved by 50%. Now… that’s a pretty good speedup by typical measures, but, then again, it’s yet another press release with yet another performance improvement. One of a dozen such releases that get issued on any given month. A good thing, to be sure, but, unless it affects you specifically, it’s something of a yawner.

Until you realized one thing: the simulator is running faster than the actual system will run.

Maybe much faster. They’re claiming that their OVPsim provides ISS speeds of 2 GIPS.

Perhaps this …

To read the full article please visit the Techfocus media site here.

Imperas CEO Interviewed by Cadence on Connecting Virtual Platforms To HW/SW Verification

Monday, August 16th, 2010

Richard Goering Interviews Simon Davidmann at DAC2010

Imperas has been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions. Simon Davidmann, Imperas CEO, talked about that work in a Cadence Design Automation Conference 2010 booth presentation, and continued the discussion afterwards in a video interview.

Imperas has taken an unusual approach to the virtual platform market - it offers models and much of its simulation and prototyping technology available for free, through the Open Virtual Platforms (OVP) initiative. Imperas also provides technology that makes it possible to analyze what’s going on in the models at run time.

To read the article and to watch the video interview please visit the Cadence site here.

To watch the video interview on YouTube go here.

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