Imperas is a Founding Member of the Cadence System Realization Alliance

THAME, United Kingdom, December 6, 2010 – Imperas™ today released its first models of the Cortex family of processor cores from ARM. Models of the M-series of cores are now available from Open Virtual Platforms™ (OVP™), including example virtual platforms incorporating the cores and support for the cores in Imperas’ advanced software development tools. Additionally, these and other models will be used by Imperas in its collaboration with Cadence Design Systems to deliver on the EDA360 vision for System Realization.

The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/ARM. The models of the ARM Cortex processor cores, as well as models of the other ARM processors including the ARM7, ARM9, ARM10 and ARM11 families, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

“Virtual platforms provide the visibility and controllability we need for our development projects,” said Christian Gehrmann of the Sweden Institute of Computer Science. “OVP, with its performance, ease of use, and library of the latest ARM processor core models, has been an excellent tool for us in our projects.”

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models. The OVP simulator also has an integration with the Eclipse IDE, enabling easy use for software developers. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“We are using OVP virtual platforms for architecture exploration and as a development vehicle for firmware,” said Maxime de Nanclas, president of Nuum Design Inc. “We found that bringing up a real time operating system and application software on our OVP virtual platform with an ARM processor core model was easier and faster than working with hardware development boards.”

Imperas, which is a member of the ARM Connected Community, is making the new OVP models of the ARM Cortex M-series, including the popular ARM Cortex-M3 processor core, available now from the OVP website. Processor core models for other ARM Cortex cores will be available within the next 16 weeks. OVP already offers ARM developers access to models of other ARM processors, including processors which utilize the v4, v5 and v6 ARM instruction sets. OVP also has reference virtual platforms incorporating the ARM cores, including bare metal platforms, a virtual platform of an Atmel AT91sam7 processor (based on an ARM7 core), and a virtual platform of the ARM IntegratorCP development board using the ARM926EJ-S. This IntegratorCP virtual platform enables users to boot Linux in under 10 seconds on a 2GHz laptop using OVPsim™. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

Cadence recently articulated an industry vision, EDA360, which talks to application-driven system development, with System Realization being one of the three elements that the industry needs to address with new offerings and broader collaboration. Imperas has joined the Cadence System Realization Alliance; its technology, including OVP and Imperas’ advanced software development tools, has been integrated with Cadence Incisive Enterprise Simulator and Incisive Software Extensions products, to better address the growing need for software development with robust verification.

“Addressing system development needs will require collaboration and partnerships, and we are excited to have Imperas as a member of the System Realization Alliance,” said Michał Siwiński, group director of product management for System Realization at Cadence. “Their Open Virtual Platforms technology, model creation tools and the large library of fast processor core models complements Cadence System Realization offerings to provide an effective solution for system and software development.”

“Whether we are talking about relatively simple systems based on high-end microcontrollers like the ARM Cortex M-series, or more complex multicore systems, embedded software today requires state of the art software development tools,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP, with ultrafast simulation, accelerates the development cycle and makes debug easier for software engineers. And participating in the Cadence System Realization Alliance by integrating OVP and Imperas tools with proven Cadence products helps to expand the range of solutions available to software developers.”

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website.

Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

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Open Virtual Platforms, OVP and OVPsim are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

Micrium μC/OS-II RTOS Running on ARM-Based Free Reference Platforms Available Through Open Virtual Platforms™ (OVP™)

THAME, United Kingdom, November 8, 2010 – Imperas today announced a flow with Micrium, Inc. focused on enabling more productive and higher quality embedded software development with the Micrium μC/OS-II Real-Time Operating System (RTOS). With firmware and application software development taking the majority of the resources for developing embedded systems, creating new flows for embedded software development is increasingly important. The Imperas flow with Micrium’s μC/OS-II makes it easier to use the Open Virtual Platforms (OVP) open source models for the development of embedded systems.

Nuum Design developed a demonstration of the OVP- μC/OS-II flow with an avionic application, available through the Nuum page on the OVP website, consisting of a flight management system for an Unmanned Aerial Vehicle (UAV). This demo system was built on a virtual prototype consisting of an ARM7 processor core, UART, timer and a math co-processor implementing the CORDIC (COordinate Rotation Digital Computer) algorithm commonly used in navigation systems. Nuum Design, who is also expert with Micrium products, ported the μC/OS-II RTOS on the virtual platform and met the application requirements to support avionic-certified RTOS. A navigation screen is part of the demo applications, displaying the UAV flight parameters, and traces GPS coordinates onto Google Earth in real-time. “Thanks to OVP, we were able to prove that using virtual platform technologies to design embedded systems is productive in avionics systems. As a result, Nuum sees OVP as an asset that promotes Nuum’s mission to help companies adopt ESL technologies,” said Maxime de Nanclas, CEO of Nuum Design. This virtual platform can be requested from Nuum Design. Developers interested in the μC/OS-II RTOS can get that from the Micrium website.

“Software is the key differentiator for today’s embedded systems, and we need to make it easier to develop embedded systems,” said Jean Labrosse, president of Micrium. “Virtual platforms are fast becoming accepted by mainstream developers as an excellent way to accelerate software development, and we are excited that Imperas and Nuum Design have provided a flow that enables users to run our μC/OS-II RTOS on OVP virtual platforms.”

A virtual platform is a set of models and a simulation engine that enables the same software binaries that would run on the hardware to be executed on a software, or virtual, platform. Because instruction-accurate models do not require the full implementation details of the hardware, they can be more easily and quickly developed, enabling software development to start months before any hardware is available. In addition, software development on virtual platforms offers the benefit of simulation of any system: full visibility and controllability, unlike the limited access that hardware provides as a software development environment. Further benefits of virtual platforms include real-time simulation speed of hundreds of millions of instructions per second, and deterministic behavior, enabling simulation runs to be repeated.

“We use the μC/OS-II RTOS on Open Virtual Platforms virtual platforms with ARM 7 and ARM 9 processor core models,” said Andreas Gerstlauer, assistant professor of Electrical and Computer Engineering at the University of Texas at Austin. “We’ve found OVP virtual platforms to be fast and easy to use, and a great tool for embedded systems research. That the models are open source is an added benefit.”

“Software simulation, or virtual platforms, are becoming a commonly used tool for embedded software development,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Making it easier to get started with virtual platforms by providing support for the most popular operating systems such as μC/OS-II provides great value to the OVP and embedded systems communities.”

The Nuum Design demo of the μC/OS-II RTOS running on a OVP virtual platform can be viewed at the Micrium booth number 517 at the ARM TechCon conference November 9-11 at the Santa Clara Convention Center. Please contact Imperas at info@imperas.com to set up an appointment.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

Open Virtual Platforms, OVP and OVPsim are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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Fast Models Developed Under MIPS-Verified™ Program

THAME, United Kingdom, September 27, 2010 – Imperas today released models of the new MIPS32® 1074K™ Coherent Processing System (CPS) from MIPS Technologies, Inc., including example virtual platforms incorporating both the MIPS32 1074Kc™ and 1074Kf™ cores and support for the cores in Imperas’ advanced software development tools. MIPS Technologies has verified the functionality of these models under the MIPS-Verified™ program.

The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS. The models of the MIPS® processor cores, as well as models of the other MIPS processors, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

“An early start to software development is critical for customer success on the advanced SoCs that will be based around our new 1074K CPS, which offers industry-leading speed for fully-synthesizable multicore IP. Having MIPS-Verified support from Imperas and OVP, the leading independent supplier of fast processor core models, enables our customers to get started immediately with their designs based on the 1074K CPS,” said Art Swift, vice president of marketing and business development, MIPS Technologies.

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP processor models. The OVP simulator also has integration into an Eclipse IDE, enabling easy use for software developers. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“State of the art multicore processors such as the 1074K CPS require state of the art software development tools,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP, with ultrafast simulation, accelerates the development cycle and makes debug easier for software engineers.”

OVP offers MIPS developers access to the 1074K CPS models, as well as access to models of other MIPS processors, including the MIPS32 4K®, 24K®, 34K®, 74K®, 1004K™ and M14K™ families of cores. OVP also has reference virtual platforms incorporating the MIPS cores, including bare metal platforms and a virtual platform of the MIPS Malta™ development board. This Malta virtual platform enables users to boot Linux in under 5 seconds on a 2GHz laptop using OVPsim, and to boot multicore SMP (Symmetric Multi-Processor) Linux in less than 8 seconds. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

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MIPS, MIPS32, M14K, 4K, 24K, 34K, 74K, 1004K, 1074K, MIPS-Verified, Malta and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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New release includes MIPS-Based SystemC TLM-2.0 Reference Platform

THAME, United Kingdom, June 22, 2010 – Imperas, which through the Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has become the de facto source for instruction accurate processor modeling and simulation, today announced a major release of new technology. Highlights of this June 2010 release are the virtual platform simulator OVPsim, which has improved its industry leading performance by 50 percent; fast models of PowerPC processors, and a MIPS-based reference platform under SystemC/TLM-2.0 which boots both Linux and Mentor Graphic’s Nucleus RTOS.

OVPsim, which for basic instruction set simulation of processors achieves over 2 billion instructions per second (or over 2,000 MIPS), achieves hundreds of MIPS performance for real world virtual platforms. ARM and MIPS-based virtual platforms can boot Linux in less than 5 seconds on a 2GHz laptop with OVPsim.

“Virtual platforms are providing significant benefits to our software team, as they make it easier to maintain existing software and develop new applications for existing avionics systems” said Dan Radke, USAF, 559th Software Maintenance Squadron. “Key attributes of virtual platforms are realizing far greater speed of software simulation, especially for multiprocessor systems, having more standard approaches to develop models to, and being able to use open source models of processors and peripherals already available, making it easier for us to build our own efficient models of complete avionics systems.”

The addition of the models of the PowerPC cores brings OVP to nearly 50 different models of processor cores, all running at very high speed, and all working with both the OVP and Imperas simulators. All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms, such as OS and CPU-aware tracing, profiling code analysis, and multicore debug.

“The first questions from our customers are always about simulation speed and model availability,” said Umesh Sisodia, founder and CEO of CircuitSutra. “Even before this release, OVP made it easy to answer those questions, but these additions to OVP for simulation speed, additional models and the TLM-2.0 reference virtual platform make OVP even easier to use and adopt.”

Reference virtual platforms provide a known good starting point for users looking to develop their own virtual platforms. OVP has released a reference virtual platform of the MIPS Malta board, running under SystemC/TLM-2.0, that boots either Linux or the Mentor Graphics Nucleus RTOS. This virtual platform can be used to understand the operating systems, since the virtual platform simulation can provide more visibility and controllability than just executing and debugging on the hardware itself. The virtual platform can also be used for the development of applications running under Linux or Nucleus on a MIPS-based system. Moreover, the virtual platform is open source, and it’s easy to add peripherals to the virtual platform using SystemC/TLM-2.0 models and develop drivers for those peripherals.

“Our licensees are focused on speeding time-to-market and extracting the highest possible performance from their SoCs,” said Art Swift, vice president of marketing for MIPS Technologies. “Virtual platforms give users a head start in the development cycle. Having a virtual platform of a common development board running at real time speeds can potentially shave weeks or months off of a typical development cycle.”

“We founded OVP 2 years ago to provide the infrastructure technology – simulation and models – to the embedded software community,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Over this time we’ve seen the community – users, tool developers, processor IP vendors, service providers, academia – come together around OVP to help them with embedded software development. We’re proud and excited to be part of this industry momentum, and to continue to contribute to OVP.”

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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Open Source Models Available Now for Free on OVP Website

THAME, United Kingdom, June 8, 2010 – Imperas, which through the Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has become the de facto source for instruction accurate processor modeling and simulation, today announced the release of fast models of PowerPC processors. These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance reaching over one thousand million instructions per second (MIPS). The models are free and available as open source from the OVP website.

The addition of the models of the PowerPC cores brings OVP to nearly 50 different models of processor cores, all running at very high speed, and all working with both the OVP and Imperas simulators. All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms, such as OS and CPU-aware tracing, profiling code analysis, and multicore debug.

“The Power Architecture is an important embedded processor family,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Users have been asking for fast models of the PowerPC processor cores, and we’re now able to deliver these models, open source and free, through Open Virtual Platforms. This is just a continuation of the momentum in the OVP initiative.”

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.
Fast Instruction accurate models are available from the OVP website for MIPS, ARM, Virage ARC, NEC v850, Power Architecture, OpenCores, SPARC and other processor families.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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Mentor Graphics Nucleus RTOS Running on ARM and MIPS-Based Free Reference Platforms Available Through Open Virtual Platforms (OVP)

THAME, United Kingdom, May 24, 2010 – Imperas today announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded™ software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus RTOS and EDGE products, makes it easier to use the Open Virtual Platforms (OVP) open source models for the development of embedded systems.

The initial result of this flow is the release of free reference virtual platforms by Imperas based on ARM and MIPS processor cores, running the Mentor Nucleus RTOS. These reference virtual platforms are available from the Open Virtual Platforms (OVP) website, www.OVPworld.org/Nucleus. The reference virtual platforms constructed from OVP open source models make it easy for embedded systems developers to use these platforms as a starting point for building their own virtual platforms. A compiled version of the Mentor Nucleus RTOS running on the reference platforms is available for demonstration. Developers interested in using the Nucleus product will need to get a license from Mentor.

“Embedded software is the key differentiator for today’s products and we need to make it easier for people to develop embedded systems,” said Glenn Perry, general manager of Mentor Graphics Embedded Software Division. “Virtual platforms are one way to accelerate software development, and we are excited that Imperas has provided a flow that enables users to run Nucleus RTOS and EDGE on OVP reference platforms.”

A virtual platform is a set of models and a simulation engine that enables the same software binaries that would run on the hardware to be executed on a software, or virtual, platform. Because instruction-accurate models do not require the full implementation details of the hardware, they can be more easily and quickly developed, enabling software development to start months before any hardware is available. In addition, software development on virtual platforms offers the benefit of simulation of any system: full visibility and controllability, unlike the limited access that hardware provides as a software development environment. Further benefits of virtual platforms include real-time simulation speed of hundreds of millions of instructions per second, and deterministic behavior, enabling simulation runs to be repeated.

“Just as we cannot imagine developing hardware without using simulation, software simulation, or virtual platforms, are moving into the mainstream of embedded software development for SoCs (systems on chips),” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Making it easier to get started with virtual platforms by releasing reference platforms with the most popular operating systems such as Nucleus RTOS provides great value to the OVP and embedded systems communities.”

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

Mentor Graphics and Nucleus are registered trademarks and Mentor Embedded is a trademark of Mentor Graphics Corporation. MIPS, Malta and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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Fast Models Developed Under MIPS-Verified™ Program

THAME, United Kingdom, March 31, 2010 – Imperas today released models of the new MIPS32® M14K™ and M14Kc™ processor cores from MIPS Technologies, Inc., including example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools. The M14K family of processors is the first to support the new microMIPSTM code compression instruction set architecture (ISA) from MIPS Technologies, which is fully supported in the Imperas models. MIPS Technologies has verified the functionality of these models under the MIPS-Verified™ program.

The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS/M14K. The models of the MIPS® processor cores, as well as models of the other MIPS processors, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

“The M14K cores and the microMIPS ISA represent groundbreaking technology for microcontrollers and other low footprint embedded applications, where performance requirements together with cost and silicon size limitations are driving our customers,” said Sandeep Vij, president and CEO, MIPS Technologies. “Having MIPS-Verified support from Imperas and OVP, the leading independent supplier of fast models of processor cores, enables our customers to get started immediately with designs leveraging M14K cores.”

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models. The OVP simulator also has an Eclipse IDE integration, enabling easy use for software developers. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“Complex systems and performance and quality requirements demand that developers have state of the art software development tools,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP was founded to enable users to have fast simulation and other tools for software development, thus accelerating the development cycle.”

OVP offers MIPS developers access to the M14K models, as well as access to models of other MIPS processors, including the MIPS32 4K®, 24K®, 34K®, 74K® and 1004K™ families of cores. OVP also has reference virtual platforms incorporating the MIPS cores, including bare metal platforms and a virtual platform of the MIPS Malta™ development board. This Malta virtual platform enables users to boot Linux in under 5 seconds on a 2GHz laptop using OVPsim. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

MIPS, MIPS32, M14K, M14Kc, 4K, 24K, 34K, 74K, 1004K, Malta and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.
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OVP Continues to Build Momentum as the De Facto Source of Fast Processor Models

THAME, United Kingdom, March 23, 2010 – The Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has announced the release of models of Virage Logic’s ARC processor cores. Models of the Virage Logic ARC® 600 and ARC® 700 families of processor cores have been released, including the ARC® 605. Additionally, Virage Logic and Imperas have cooperated on the verification of the functionality of the models. Virage Logic’s ARC line of processor cores, the world’s second most widely used processor architecture, are commonly used in audio and video subsystems, and in flash controllers, among other applications. These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance reaching hundreds of millions of instructions per second. The models are free and available as open source from the OVP website.

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models.

“Imperas is moving the embedded systems industry forward with its visionary approach to virtual platforms and the easy accessibility of OVP,” said Dr. Yankin Tanurhan, vice president and general manager, processor and NVM solutions, for Virage Logic. “Verifying the compatibility and functionality of these high-performance models of our ARC processors and making them freely available is a huge advantage for design teams worldwide. This availability will help enable them to develop high-quality software faster and more easily using virtual platform models of their complete SoCs and embedded systems.”

“As the semiconductor industry’s trusted IP partner, Virage Logic recognizes the importance of freely available models to enable rapid growth and accelerate the design and programming of embedded systems on chip,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Compatibility and quality of models is essential when using virtual platforms to develop software. Offering free, verified processor models means developers can get higher quality software developed faster and help close the software gap.”

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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ARM Integrator Virtual Platform Speeds Embedded Software Development

THAME, United Kingdom, February 22, 2010 – The Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has announced the release of a reference virtual platform of the ARM Integrator development board using OSCI SystemC TLM-2.0 C++. This virtual platform includes all the models needed for the virtual platform to enable users to run Linux. The virtual platform can be executed either in the OVP simulator (OVPsim), or in a SystemC/TLM-2.0 simulation environment using any of the industry SystemC/TLM-2.0 simulators. The virtual platform and all models are free and available as open source from the OVP website.

“We have used the ARM Integrator virtual platform available from OVP to help our customers understand how Linux and drivers worked on their hardware,” said Dave Von Bank, president of Posedge Software, a consulting company for embedded software engineering. “We’re happy to use and contribute to the OVP open source initiative for embedded software development.”

The OVP ARM Integrator virtual platform can be used to understand the Linux operating system running on the development board, since the virtual platform simulation can provide more visibility and controllability than just executing and debugging on the hardware itself. The virtual platform can also be used for the development of applications running under Linux on an ARM-based system. Moreover, the virtual platform is open source, and it’s easy to add peripherals to the virtual platform using SystemC/TLM-2.0 models and develop drivers for those peripherals.

“For my course on System-on-Chip (SoC) Design, students learn about both hardware and software development aspects,” said Professor Andreas Gerstlauer of the Electrical and Computer Engineering Department at the University of Texas at Austin. “We eventually implement a software defined radio design on an ARM-based FPGA prototyping board. I have found the Open Virtual Platforms models allow my students to simulate the software, from drivers to applications running on top of the Linux OS. We use the OVP models in a SystemC/TLM-2.0 simulation environment, and find them fast and easy to use. That the models are open source and come with excellent documentation and support is an added benefit.”

“Virtual platforms make software development easier and more efficient,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “It’s great that students and software developers can have free access to use models that run at real-time speeds in industry standard simulation environments.”

The ARM Integrator virtual platform includes the OVP model of the ARM926EJ-S processor core, which runs at hundreds of millions of instructions per second (MIPS), as well as models of the other peripherals on the ARM Integrator development board. The virtual platform utilizes host workstation resources for keyboard and display. This virtual platform can be run in either OVPsim or SystemC/TLM-2.0 simulators, and in either simulation environment boots Linux in less than 10 seconds.

Open Virtual Platforms (www.OVPworld.org)
OVP, which is quickly becoming the de facto source for fast models of processors, includes the OVPsim simulator, libraries of models and APIs for developing new models. OVPsim executes platforms, including multicore platforms, at hundreds of millions of instructions per second, providing the speed that software developers require for simulation of embedded systems. Model libraries include everything from models of individual processors (over 40 available for ARC, ARM, MIPS, NEC and OpenCores) and component models to more complex platforms, such as ARM IntegratorCP and MIPS Malta development boards for running Linux. All OVP processor models include a SystemC/TLM-2.0 interface for easy integration in those virtual platform environments. OVP APIs enable the embedded software community to develop models of processors, behavioral components and peripherals, and to connect these together into virtual platforms that run the final target system software binaries unchanged. Since its founding in early 2008, over 2,100 people have registered on the OVP website.

About the OVP Initiative (www.OVPworld.org)
The OVP initiative was founded with a donation by Imperas of approximately $4 million of simulation infrastructure. The goal of organization is to help the industry to build an effective multi-core development infrastructure through the use and adoption of open virtual platform technology. The website serves as a portal for OVP members covering details about the technology, providing a discussion forum for the community, and links to download each component. The technology has the support of electronic design automation (EDA) companies, end users and intellectual property (IP) providers. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

About Imperas (www.imperas.com)
Imperas provides methodologies, technologies and products to enable the efficient and effective verification of software functionality and software performance for embedded systems. Its products enable software functional verification, performance profiling, and analysis for embedded software operating on multiprocessor MPSoCs. With an engineering base in the United Kingdom, Imperas distributes its products to customers worldwide. For more information, visit www.imperas.com.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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Models of MIPS™ 74K™ Processor and 1004K™ Multicore Processor Developed Under MIPS-Verified™ Program

THAME, United Kingdom, February 17, 2010 – The Open Virtual Platforms (OVP) initiative (www.OVPworld.org), has released new models of MIPS Technologies, Inc. processor cores and continues its move to becoming the de facto source of fast models. The MIPS 74K and 1004K processors are the most advanced cores from MIPS, with the 1004K being a multi-core, multi-threaded processor, with up to 4 cores and 2 threads per core. MIPS has verified the functionality of these models under the MIPS-Verified program. These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance of hundreds of millions of instructions per second.

Embedded software complexity is increasing rapidly, especially with multicore and multi-threaded processors like the MIPS 1004K being utilized for embedded systems. This complexity, and associated problems with software schedules and bugs, drives users to start development earlier in the project. Early simulation of software with OVP technology provides benefits of both increased productivity and increased quality.

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, the tools they need for a more robust development environment. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models.

“Bringing simulation to software development is a natural step to an earlier start to software development, and better debugging and analysis of multicore software. Bringing low cost simulation tools and free, fast models of state of the art processors such as the MIPS 74K and 1004K is why we founded Open Virtual Platforms.,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP now has the full range of MIPS32 cores available as fast models. OVP is rapidly becoming the de facto place to source fast models.”

Open Virtual Platforms (www.OVPworld.org)
OVP includes the OVPsim simulator, libraries of models and APIs for developing new models. OVPsim executes platforms, including multicore platforms, at hundreds of millions of instructions per second, providing the speed that software developers require for simulation of embedded systems. Model libraries include everything from individual processor models (from ARC, ARM, MIPS and OpenCores) and component models to more complex platforms, such as ARM IntegratorCP and MIPS Malta development boards for running Linux. All OVP processor models include a SystemC/TLM-2.0 interface for easy integration in those virtual platform environments. OVP APIs enable the embedded software community to develop models of processors, behavioral components and peripherals, and to connect these together into virtual platforms that run the final target system software binaries unchanged. Since its founding in early 2008, over 2100 people have registered on the OVP website.

About the OVP Initiative (www.OVPworld.org)
The OVP initiative was founded with a donation, by Imperas, of approximately $4 million of simulation infrastructure. The goal of organization is to help the industry to build an effective multi-core development infrastructure through the use and adoption of open virtual platform technology. The website serves as a portal for OVP members covering details about the technology, providing a discussion forum for the community, and links to download each component. The technology has the support of electronic design automation (EDA) companies, end users and intellectual property (IP) providers. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

About Imperas (www.imperas.com)
Imperas provides methodologies, technologies and products to enable the efficient and effective verification of software functionality and software performance for embedded systems. Its products enable software functional verification, performance profiling, and analysis for embedded software operating on multiprocessor MPSoCs. With an engineering base in the United Kingdom, Imperas distributes its products to customers worldwide. For more information, visit www.imperas.com.

Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.
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