OVP Fast Processor Models Developed Under MIPS-Verified(tm) Program

OXFORD, United Kingdom, May 10, 2012 - Imperas(tm) is releasing the Open Virtual Platforms(tm) (OVP(tm)) Fast Processor Models for MIPS Technologies new Aptiv(tm) Generation of processor cores. Example virtual platforms are also being released, as well as support for the cores in Imperas M*SDK(tm) advanced software development tools. MIPS Technologies has verified the functionality of the Aptiv models under the MIPS-Verified(tm) program.”

The processor core models and example platforms are available from the Open Virtual Platforms website, http://www.OVPworld.org/MIPS. The models of the Aptiv processor cores, as well as models of other MIPS(R) processors, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

“Our new Aptiv Generation of cores pushes the boundaries in performance and efficiency. Having MIPS-Verified support from Imperas and OVP, a leading supplier of high-quality, fast processor core models, enables our customers to get started immediately with designs based on the Aptiv Generation cores,” said Giddy Intrater, vice president of marketing, MIPS Technologies. .

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP processor models. The OVP simulator also has integration into an Eclipse IDE, enabling easy use for software developers. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

The OVP library of Fast Processor Models includes the complete families of the ARMv4, ARMv5, and ARMv6 architecture-based processors, as well as models of most of the processors in the ARM Cortex-M series and Cortex-A series processors. In addition to working with the OVP simulator, these models work with the Imperas Multiprocessor/Multicore Software Development Kit, M*SDK, which includes advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“State of the art processor cores, especially multicore processors, such as these new Aptiv cores from MIPS require state of the art software development tools,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP Fast Processor Models, which are faster, more accurate and easier to use than other models, accelerates the development cycle and makes debug and optimization easier for software engineers.”

OVP offers MIPS developers access to all of the MIPS32(R) 32-bit processor models, including the MIPS32 4K, 24K, 34K, 74K, 1004K, 1074K and M14K families of cores. OVP also has reference virtual platforms incorporating the MIPS cores, including bare metal platforms and a virtual platform of the MIPS Malta development board. This Malta virtual platform enables users to boot Linux in under 5 seconds on a 2GHz laptop using OVPsim, and to boot multicore SMP (Symmetric Multi-Processor) Linux in less than 8 seconds. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

In addition to working with the OVP simulator OVPsim, the OVP Fast Processor Models work with the Imperas Multiprocessor/Multicore/Multithread Software Development Kit (M*SDK). These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis. The M*VAP (Verification, Analysis and Profiling) tools utilize the Imperas SlipStreamer(tm) patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

Open Virtual Platforms, OVP, OVPsim, SlipStreamer, M*SDK and M*VAP are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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OVP Ease of Use, Fast Processor Model of ARM Processor Key in Decision Process

OXFORD, United Kingdom, March 26, 2012 - NEPHRON+, an EU research project, has recently selected Open Virtual Platforms™ (OVP™) tools for its software and test development environment. Key factors in its decision were ease of use and flexibility of OVP, as well as the availability of ARM® processor models chosen for the electronics system.

The NEPHRON+ project is developing a wearable artificial kidney and personal renal care system. According to Frank Poppen of OFFIS - Institute for Information Technology of Germany, the lead institution in the consortium for the embedded software development, “OVP was selected because of the ease with which models are built and the flexibility in interfacing to other tools.” He continued, “The availability of the ARM processor model we needed, and the open source nature of the OVP models, were also important factors.”

One of OFFIS’s development milestones was to interface the OVP simulator, OVPsim, to the Simulink system simulator. This was done to enable testing of the target software, running directly on the processor in the virtual platform, with the full system environment. Due to the open nature of the OVP technology, OFFIS was able to write its own interface model, which is now available on the OFFIS website (http://system-synthesis.org/offissimlink).

“OVP is addressing key issues in software development for embedded systems,” said Noel Hurley, VP Business Development, ARM. “By supporting the creation of virtual platforms, OVP is enabling early software development and helping expand the ARM user community.”

OVP processor models are instruction accurate, and very fast. They enable the early creation of software development environments for embedded software developers looking to create hardware-dependent software such as firmware and bare metal applications. OVP processor models employ a state of the art just-in-time code morphing engine to accelerate simulation speeds. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models. The processor models can also be integrated into SystemC/TLM2 based virtual platforms using the native TLM2 interface available with all OVP models. The native TLM2 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

The OVP library of Fast Processor Models includes the complete families of the ARMv4, ARMv5, and ARMv6 architecture-based processors, as well as models of most of the processors in the ARM Cortex™-M series and Cortex-A series processors. In addition to working with the OVP simulator, these models work with the Imperas Multiprocessor/Multicore Software Development Kit, M*SDK, which includes advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“ARM users recognize the importance of virtual platforms to accelerate the development of software for embedded systems,” said Simon Davidmann, Imperas CEO, and OVP founding director. “Compatibility and quality of models is essential when using virtual platforms to develop software, and having validated processor models available for free from OVP means developers can get higher quality software developed faster. Validated models really help to close the Software Gap.”

Available OVP Fast Processor Models of ARM cores

The following specific models are available as open source from OVP:

ARM7TDMI®, ARM720T™, ARM7EJ-S™

ARM920T™, ARM922T™, ARM926EJ-S™, ARM940T™, ARM946E™, ARM966E-S™, ARM968E-S™

ARM1020E™, ARM1022E™, ARM1026EJ-S™

ARM1136J-S™, ARM1156T2-S™

Cortex-A5 (Single Core), Cortex-A8, Cortex-A9 (Single core), Cortex-A9 MPCore™

Cortex-M3, Cortex-M4

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

About NEPHRON+ (www.nephronplus.eu)

For more information about the NEPHRON+ EU research project, please go to the respective website.

Open Virtual Platforms, OVP and OVPsim are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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OVP Model of ARM Cortex-A9 MPx2 is at the Heart of the Cadence Zynq Virtual Platform

OXFORD, United Kingdom, October 26, 2011 – Imperas™, which is a member of the ARM Connected Community, has released its models of the Cortex-A9 MPCore and Cortex-A5 UP ARM processor cores, including the 1, 2, 3 and 4-core versions of the Cortex-A9 MPCore. Models of the Cortex-A9 MPCore and Cortex-A5 UP are now available from Open Virtual Platforms™ (OVP™), including example virtual platforms incorporating the cores and support for the cores in Imperas’ advanced software development tools.

These OVP Fast Processor Models are in use by customers, an example being the inclusion of the model of the Cortex-A9 MPx2 in the Cadence-developed Virtual Platform of the Xilinx Zynq-7000 Extensible Processing Platform (EPP). The Zynq-7000 EPP Virtual Platform was announced earlier today by Cadence and Xilinx and also discussed in a blog post.

Imperas earlier this week announced the interoperability of its OVP Fast Processor Models and advanced software Multiprocessor/Multicore Verification, Analysis and Profiling (M*VAP™) tools with the Cadence Virtual System Platform. Imperas also announced earlier this week the development of the OVP Fast Processor Model of the Xilinx MicroBlaze soft processor core. This model of the Xilinx MicroBlaze will be available with certain versions of the Zynq-7000 EPP Virtual Platform as an extension to the virtual platform.

“ARM’s Cortex processor cores are at the heart of leading edge SoCs and embedded systems,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “And the Imperas OVP Fast Processor Models are at the heart of the virtual platforms of these SoCs and systems.”

The OVP Fast Processor Models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org Cortex-A web page. The models of the ARM Cortex-A9 MPCore and Cortex-A5 UP, as well as models of the other ARM processors including the ARM7, ARM9, ARM10, ARM11, Cortex-A and Cortex-M families, work with the Imperas and OVP simulators, and have shown exceptionally fast simulation performance of hundreds of millions of instructions per second. The OVP Fast Processor Models include support for both the 32 and 16-bit instructions, as well as the MMU, MPU, TCM, VFP and NEON features.

Open Virtual Platforms, with over 75 Fast Processor Models, has become the de facto source for instruction accurate models of processor cores. All OVP Fast Processor Models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP processor models employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models. The native TLM-2.0 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

In addition to working with the OVP simulator OVPsim™, the OVP Fast Processor Models work with the Imperas Multiprocessor/Multicore/Multithread Software Development Kit (M*SDK™). These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis. The M*VAP™ tools utilize the Imperas SlipStreamer™ patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

Available OVP Fast Processor Models of ARM cores

The following specific models are available as open source from OVP:

ARM7TDMI, ARM720T, ARM7EJ-S

ARM920T, ARM922T, ARM926EJ-S, ARM940T, ARM946E, ARM966E-S, ARM968E-S

ARM1020E, ARM1022E, ARM1026EJ-S

ARM1136J-S, ARM1156T2-S

Cortex-A5 UP, Cortex-A8, Cortex-A9 UP, Cortex-A9 MPCore

Cortex-M3, Cortex-M4

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from www.OVPworld.org/quotes.

# # #

Imperas, Open Virtual Platforms, OVP, OVPsim,,SlipStreamer, M*SDK and M*VAP are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

Imperas Joins Xilinx Alliance Program

OXFORD, United Kingdom, October 24, 2011 - Imperas™ today announced that a model of the Xilinx MicroBlaze™ soft processor core has been developed, and is being provided through the Open Virtual Platforms™ (OVP™) website. The OVP Fast Processor Model™ and example virtual platforms including the MicroBlaze core are available from the Open Virtual Platforms website, www.OVPworld.org/XILINX. Imperas also announced that they have joined the Xilinx Alliance Program, helping to expand the Xilinx embedded ecosystem with the MicroBlaze model, and their virtual platform and software development tools.

Xilinx has supported Imperas with technology to assist in the verification of the OVP Fast Processor Model of the MicroBlaze. “Imperas, with its OVP Fast Processor Models and software development tools, is addressing key issues in software development for embedded systems,” said Mark Jensen, director, processor platforms marketing for Xilinx. “We are excited to work with Imperas to ensure that high quality models are easily available to our customers worldwide, helping them to develop and test software faster and more efficiently using virtual platforms.”

The model of the MicroBlaze core works with both the Imperas and OVP simulators, and has shown exceptionally fast simulation performance of hundreds of millions of instructions per second. Users are able to use the MicroBlaze model as a standalone processor, or add peripheral models to it to more fully model their FPGAs. Users could even combine the MicroBlaze model with the OVP Fast Processor Model of the ARM Cortex-A9MPx2 to create their own virtual platform of the Zynq™-7000 Extensible Processing Platforms with a MicroBlaze core implemented in the FPGA fabric.

“We’ve been using OVP for embedded software development and system bring up,” said Maxime de Nanclas, CEO of Nuum Design. “We’re also Xilinx MicroBlaze users, and are excited to be able to use these technologies together to enable us to complete our projects faster and with fewer bugs.”

“Imperas is very excited to be working with Xilinx, the leading provider of programmable platforms,” said Simon Davidmann, president and CEO, Imperas and founding director of OVP. “As Xilinx products enable even more complex embedded systems to be implemented in their FPGAs, providing the Xilinx user community with state of the art software development tools becomes even more valuable for success.”

All OVP Fast Processor Models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP Fast Processor Models employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM2 based virtual platforms using the native TLM2 interface available with all OVP models. The native TLM2 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

In addition to working with the OVP simulator OVPsim™, the OVP Fast Processor Models work with the Imperas Multiprocessor/Multicore/Multithread Software Development Kit (M*SDK™). These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis. The Verification, Analysis and Profiling (M*VAP™) tools utilize the Imperas SlipStreamer™ patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

The OVP Fast Processor Model of the MicroBlaze soft processor core will be fully released before the end of year. To see a demo, or to participate in the beta program, please contact Imperas directly, or through the MicroBlaze page on the OVP website, www.OVPworld.org/XILINX.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

# # #

Imperas, Open Virtual Platforms, OVP, OVP Fast Processor Models, OVPsim, M*SDK, M*VAP and SlipStreamer are trademarks of Imperas Software Limited. MicroBlaze and Zynq are trademarks of Xilinx, Inc. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

Imperas Collaborates with Cadence to Address Critical Software Development Issues

OXFORD, United Kingdom, October 24, 2011 - Imperas™ today announced that its Open Virtual Platforms™ (OVP™) Fast Processor Models have been validated with the Cadence® Virtual System Platform for creation of high performance software development platforms. In addition, the Imperas tools for Multiprocessor/Multicore/Multithread Verification, Analysis and Profiling (M*VAP™) operate with Virtual System Platform, together providing a robust set of tools for embedded software development as part of the Cadence System Development Suite.

The Fast Processor Models are available from the Open Virtual Platforms website, www.OVPworld.org. Models available include the ARC 6xx/7xx families, ARM 7, 9, 10, 11, Cortex-M and Cortex-A families, MIPS Technologies 4K, 24K, 34K, 74K, 1004K, 1074K and M14K families, Power Architecture E200 cores and Renesas (NEC Electronics) V850 cores. All OVP Fast Processor Models have shown exceptionally fast performance of hundreds of millions of instructions per second.

The M*VAP tools utilize the Imperas SlipStreamer™ patent pending binary interception technology. SlipStreamer enables analytical tools - tracing, profiling, code coverage, memory analysis and more - to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

“High performance processor models are an important part of our virtual prototype solution,” said Michał Siwiński, group director of product marketing, System & Software Realization Group, Cadence. “The Open Virtual Platforms library of fast processor core models, together with Imperas tools for software analysis, complement the Virtual System Platform to provide an effective solution for system and software development.”

All OVP Fast Processor Models are instruction accurate, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these Imperas OVP Fast Processor Models can be created with the Virtual System Platform system creation tools, and utilize the native TLM2 interface available with all OVP models.

The OVP Fast Processor Models enable the use of the Imperas M*VAP tools within the Virtual System Platform environment. These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis.

“Software development is the critical path for the delivery of embedded systems. Whether we are talking about complex multicore systems, or relatively simple systems based on high-end microcontrollers, embedded software today requires state of the art software development tools,” said Simon Davidmann, president and CEO, Imperas. “Virtual System Platform addresses these issues by easing the task of virtual platform development and enabling unified hardware/software debugging. In combination with the Imperas OVP fast processor models and M*VAP tools this provides a powerful environment for embedded software development.”

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

# # #

Imperas, Open Virtual Platforms, OVP, M*VAP and SlipStreamer are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

OVP Fast Processor Models Being Used For Automotive Electronics Software Testing

OXFORD, United Kingdom, October 12, 2011 – Imperas™ today announced that Imperas and Renesas Electronics Corporation (TSE: 6723) have been cooperating on the verification of the Open Virtual Platforms™ (OVP™) Fast Processor Models of the Renesas V850 cores. These models are being used with the OVPsim™ virtual platform simulator, usually for software testing of automotive electronics applications. Users include NIRA Dynamics, a provider of tire pressure sensor systems.

Renesas and Imperas collaborated on the verification plan for the OVP Fast Processor Models™ of the V850 Family of CPU cores, and Renesas has supported Imperas with technology to assist in the verification of the OVP Fast Processor Models. “Imperas with its OVP Fast Processor Models is addressing key issues in software development for embedded systems,” said Hirohiko Ono, senior manager of the MCU Tools Marketing Department for Renesas Electronics Corporation. “We are happy to work with Imperas to ensure that high quality models are easily available to our worldwide customers, helping them to develop and test software faster and more easily using virtual platforms.”

“In the automotive electronics industry we always need to do more testing of our embedded systems software,” said Peter Lindskog, head of development for NIRA Dynamics AB, a subsidiary of Audi Electronics Venture GmbH. “Finding that the simulation performance of the Imperas/OVP V850 model was 50 times faster than our previous solution opens up new possibilities for us in software testing, and enables us to increase our test coverage and product reliability,”

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP processor models work with the OVPsim and Imperas simulators, which employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM2 based virtual platforms using the native TLM2 interface available with all OVP models. The native TLM2 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

“Imperas is very excited to be working with Renesas, the leader in automotive MCUs,” said Simon Davidmann, president and CEO, Imperas. “Cooperation between processor vendors and independent tool developers is critical to providing optimized flows for embedded software development.”

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

# # #

Imperas, Open Virtual Platforms, OVP and OVP Fast Processor Models are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

OVP Fast Processor Models are Fast, Easy to Use in SystemC Environments

OXFORD, United Kingdom, October 12, 2011 – hd Lab, Inc., the leading independent design solution provider and training company in Japan, recently selected Open Virtual Platforms™ (OVP™) tools for both development of instruction accurate virtual platform models and for use in part of its SystemC training courses. Imperas, which through the OVP initiative (www.OVPworld.org) has become the de facto source for instruction accurate processor modeling and simulation, provides a native SystemC TLM-2.0 interface with all the Fast Processor Models, as well as providing a native OVP interface to the OVPsim simulator .

“For our SystemC training courses, we want the attendees to focus on building SystemC models, and how to use those models,” said Hiroyasu Hasegawa, chief technology officer of hd Lab. “By using OVP Fast Processor Models, which work easily in SystemC virtual platforms, students do not have to worry about processor models, and are able to get the most out of our courses. The OVP models work well in our SystemC environment and also with other SystemC tools. We are excited to be able to expand our design service offerings in virtual platforms to our customers.”

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP processor models employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM2 based virtual platforms using the native TLM2 interface available with all OVP models. The native TLM2 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

The OVP library of Fast Processor Models includes models of the complete families of the ARMv4, ARMv5, and ARMv6 instruction set based processors, as well as models of most of the processors in the Cortex M-series and Cortex A-Series. Also included are the complete families of MIPS Technologies MIPS32 and microMIPS processors, both single and multi-core, and processor core models for the Renesas Electronics V850 family.

Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM2 based virtual platforms using the TLM2 interface available with all OVP models. In addition to working with the OVP simulator, these models work with the Imperas Multiprocessor/Multicore Software Development Kit, M*SDK, which includes advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“We are excited to have such a prominent service provider, hd Lab, as our first OVP partner in Japan,” said Larry Lapides, vice president of sales for Imperas. “We have had OVP users in Japan since the launch of the initiative over three years ago, and with the significant growth in Imperas users in Japan, it is important to see the overall ecosystem also growing.”

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

Open Virtual Platforms, OVP and OVPsim are trademarks of Imperas Software Limited. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

# # #

Tokyo NanoFarm to Sell Imperas and Open Virtual Platform Products

OXFORD, United Kingdom, October 12, 2011 - Imperas™ today announced that it has named Tokyo NanoFarm LLC as its representative in Japan. Tokyo NanoFarm will be selling both the Open Virtual Platforms™ (OVP™) OVPsim simulator, as well as the Imperas Multicore/Multiprocessor Software Development Kit (M*SDK™). The OVP Fast Processor Models, with over 80 different models in the OVP library, now the de facto standard for instruction accurate, high performance models of processor cores, are available at no charge from the OVP website.

“Japan is an exciting market for embedded software, and Imperas is addressing the most critical issue, software development,” said Hidemi Yokokawa, president of Tokyo NanoFarm. “The combination of their Open Virtual Platforms, especially the OVP Fast Processor Models, and the Imperas Multicore/Multiprocessor Software Development Kit (M*SDK™), with its advanced tools for embedded software verification, analysis and debug, is a great value to bring to software developers in Japan.”

“Japan is a significant developer of embedded systems and software,” said Larry Lapides, vice president of sales for Imperas. “We have had OVP users in Japan in both the industrial and academic worlds since the launch of OVP over three years ago, and they represent a significant portion of the over 5,000 people registered on the OVP website. As we start promoting OVP and M*SDK in Japan, we are excited to have an organization of the caliber and experience of Tokyo NanoFarm representing Imperas in Japan.”

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/quotes.

# # #

Imperas, Open Virtual Platforms, OVP and M*SDK are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services

Free, Open Source Models Available From Open Virtual Platforms

OXFORD, United Kingdom, June 3, 2011 – Imperas™, which is a member of the ARM Connected Community, has released its first models of the Cortex-A family of ARM processor cores. Models of the ARM Cortex-A series of cores, along with models of the Cortex-M series of cores, are now available from Open Virtual Platforms™ (OVP™), including example virtual platforms incorporating the cores and support for the cores in Imperas’ advanced software development tools.

The OVP Fast Processor Models™ and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/ARM. The models of the ARM Cortex-A8, Cortex-A9 and Cortex-M4 processor cores, as well as models of the other ARM processors including the ARM7, ARM9, ARM10, ARM11 and Cortex-M3 families, work with the Imperas and OVP simulators, and have shown exceptionally fast simulation performance of hundreds of millions of instructions per second. The OVP Fast Processor Models include support for both the 32 and 16-bit instructions, as well as the MMU, MPU, TCM, VFP and NEON features.

“Software development, not just coding but debug, analysis and optimization, is the critical path for embedded systems based on the ARM Cortex-A8, Cortex-A9 and Cortex-M4,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “The OVP Fast Processor Models accelerate the development cycle and make debug easier for software engineers. And the Imperas M*SDK tools provide additional capabilities needed for hardware-dependent software development on state of the art SoCs.”

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP processor models employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models. The native TLM-2.0 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

In addition to working with the OVP simulator OVPsim™, the OVP Fast Processor Models work with the Imperas Multiprocessor/Multicore/Multithread Software Development Kit (M*SDK™). These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis. The Verification, Analysis and Profiling (M*VAP™) tools utilize the Imperas SlipStreamer™ patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

Imperas is making the new OVP Fast Processor Models of the ARM Cortex-A series, including the popular ARM Cortex-A8 and Cortex-A9 processor cores, and the ARM Cortex-M4, available now from the OVP website. Processor core models for the ARM Cortex-A9MP cores will be available within the next 10 weeks. OVP already offers ARM developers access to models of other ARM processors, including the Cortex-M3 and processors which utilize the v4, v5 and v6 ARM instruction sets. OVP also has reference virtual platforms incorporating the ARM cores, including bare metal platforms, a virtual platform of an Atmel AT91sam7 processor (based on an ARM7 core), and a virtual platform of the ARM IntegratorCP development board using the ARM926EJ-S or Cortex-A9. This IntegratorCP virtual platform enables users to boot Linux in under 10 seconds on a 2GHz laptop using OVPsim. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

Available OVP Fast Processor Models of ARM cores
The following specific models are available as open source from OVP:
ARM7TDMI, ARM720T, ARM7EJ-S
ARM920T, ARM922T, ARM926EJ-S, ARM940T, ARM946E, ARM966E-S, ARM968E-S
ARM1020E, ARM1022E, ARM1026EJ-S
ARM1136J-S, ARM1156T2-S
Cortex-A8, Cortex-A9
Cortex-M3, Cortex-M4

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from www.ovpworld.org/newsblog/?p=42.

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Imperas, Open Virtual Platforms, OVP Fast Processor Models, OVP, OVPsim, M*, M*SDK, M*VAP and SlipStreamer are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

New Flows Address Software Development, System Design, Co-Verification

OXFORD, United Kingdom, June 3, 2011 – Imperas™ today announced that its Open Virtual Platforms™ (OVP™) OVPsim simulator and OVP Fast Processor Models™ have been integrated with Aldec’s Hardware Emulation Solutions (HES), Cadence Design System’s Virtual System Platform and Proximus’ products. OVP’s position as the de facto source of instruction accurate processor core models provides additional value in the hardware-software co-verification, SystemC simulation, software development and system design flows supported by these tools.

The OVP Fast Processor Models and OVPsim are available from the Open Virtual Platforms website, www.OVPworld.org. The nearly 60 models available include models of the ARC 6xx/7xx families, ARM 7, 9, 10, 11, Cortex-M and Cortex-A families, MIPS Technologies 4K, 24K, 34K, 74K, 1004K, 1074K and M14K families, Power Architecture E200 cores and Renesas (NEC Electronics) V850 cores. All models have shown exceptionally fast simulation performance of hundreds of millions of instructions per second.

As SoCs have become increasingly complex, both in terms of the hardware design and the software stack delivered with the silicon, emulation of the SoC has become more widely used as a verification tool. The Aldec HES product, with its Transaction Level emulation System, integrates easily into existing RTL verification flows, providing both simulation acceleration and hardware emulation functionality.

“The integration of HES with OVPsim enables hardware and software design teams to implement virtual models of processors, memory and peripherals while the RTL modules run in the emulator board,” said Zbyszek Zalewski, general manager of Aldec’s Hardware Division. “This new integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.”

The Cadence Virtual System Platform is a software development platform that utilizes Cadence’s industry leading Incisive Verification Platform, particularly the SystemC simulation and debug environment. It adds multiple views of the hardware and software, assisting not only software development but also system analysis. The OVP Fast Processor Models have been integrated with the Virtual System Platform, not only providing simulation of the processor cores but also connecting to the Cadence debug tools. In addition, the Imperas Multicore/Multiprocessor Verification, Analysis and Profiling (M*VAP™) tools have been enabled to run in the Virtual System Platform environment. The M*VAP tool suite includes tools for embedded software development, such as code coverage, tracing, profiling and memory and cache analysis. These tools are completely non-intrusive, requiring no instrumentation or modification of the software source code, and are both CPU and OS aware.

The Proximus products together provide a suite of tools for system design and software development. These products provide an environment for analyzing the complete heterogeneous multiprocessor design at different levels of abstraction. “OVP Fast Processor Models are an essential foundation to system level design, helping to unleash innovation in this area,” said Enno Wein, founder and CEO of ProximusDA. “By providing free models and associated virtual prototyping infrastructure, OVP enables the ecosystem to focus on advanced technologies and solutions”.

All OVP Fast Processor Models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP Fast Processor Models work with the OVPsim and Imperas simulators, which employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models. The native TLM-2.0 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

“SoC development – system, hardware, software – has become an incredibly complex project,” said Simon Davidmann, president and CEO, Imperas. “One company cannot hope to address all the needs, especially as those needs are constantly evolving. By providing significant technology as Open Virtual Platforms, and creating a collaborative environment for tool vendors, IP developers, users and academics, we are contributing to the evolution of a new SoC and embedded system design methodology.”

Aldec, Cadence and Proximus will all have demos showing the integrations available for users to watch at the upcoming Design Automation Conference (DAC) in San Diego. Imperas can also be seen at DAC presenting at the North American SystemC User Group (NASCUG) on Monday June 6, and participating in a pavilion panel session on embedded operating systems on Tuesday June 7.

About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from www.ovpworld.org/newsblog/?p=42.

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Imperas, Open Virtual Platforms, OVP Fast Processor Models,  OVP, and M*VAP are trademarks of Imperas Software Limited. Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.