Uses OVP ARM Integrator platform, OVP ARM processor models and OCP-IP SystemC TLM Modeling kit

Open Core Protocol International Partnership (OCP-IP), the organization delivering a common standard for intellectual property core interfaces that facilitate “plug and play” SoC design, and CircuitSutra, experts in SystemC modeling and embedded software development, along with Imperas, the company providing the infrastructure for the future of software virtual platforms and enabling the next generation of embedded software development, today announced the availability of a Virtual Platform Demo created utilizing OCP-IP’s advanced Modeling Kit. This example platform acts as a guide to OCP-IP members enabling them to quick-start their ESL activities using the OCP-IP TLM Modeling Kit; which is fully compatible with OSCI’s TLM 2.0.1. Both the kit and Virtual Platform examples are free to both OCP-IP members and non-members.

The Virtual Platform Demo utilizes Open Virtual Platforms (OVP) technology…

For more information, please read the full press release here, or download it here.

You can get the virtual platform here, and see the OVP information here and here.

For the CircuitSutra presentation on the virtual platform visit here.

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Richard Goering Interviews Simon Davidmann at DAC2010

Imperas has been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions. Simon Davidmann, Imperas CEO, talked about that work in a Cadence Design Automation Conference 2010 booth presentation, and continued the discussion afterwards in a video interview.

Imperas has taken an unusual approach to the virtual platform market - it offers models and much of its simulation and prototyping technology available for free, through the Open Virtual Platforms (OVP) initiative. Imperas also provides technology that makes it possible to analyze what’s going on in the models at run time.

To read the article and to watch the video interview please visit the Cadence site here.

To watch the video interview on YouTube go here.

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Imperas today announced on the second anniversary of the formation of the Open Virtual Platforms initiative that the new release of its OVPsim reference simulator is now 50% faster than previous versions. This enables embedded software to be developed for ARM, MIPS, ARC, Power Architecture, and NEC processors on simulations running up to 2,000 MIPS on a standard desktop PC.

The new release also comes with new models of Power Architecture processors and also more SystemC TLM 2.0 platforms including a MIPS based Malta platform that boots Linux or Mentor Nucleus.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To find out more about OVP models, virtual platforms and operating system support, please visit the models pages.
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Imperas today announced its relationship with Mentor Graphics Embedded Software Division (ESD) and now makes available virtual platforms for ARM and MIPS processor cores that run the Mentor Nucleus RTOS.

These platforms are free to download and are provided as open source. A binary image of Nucleus 2.2 is provided to demonstrate operation. To download the self contained examples visit the library page on www.OVPworld.org/Nucleus.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To find out more about OVP models, virtual platforms and operating system support, please visit the models pages.
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Conference Coverage - Gary Smith at DVCon San Jose, March 2010, an article by Bill Murray at www.SCDsource.com

Gary Smith of GarySmithEDA presented a snapshot of the status and direction of electronic system level design (ESL) methodology at the recent Open SystemC Initiative (OSCI) SystemC day at the Design and Verification Conference (DVCon 2010) in San Jose, California. He talked about the progress of ESL, its five high value applications, market sizing and concluded with some comments about its ability to satisfy the needs of the embedded system software developer.
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Smith said “We have two killer apps down. One is ESL synthesis. …

The other one is the software virtual prototype. Synopsys has just bought nearly everyone, but Carbon and Imperas remain.”
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To read the full article, please visit http://www.scdsource.com/article.php?id=386.

An interesting indepedent blog on Imperas by Brian Bailey

With all of the acquisitions in the virtual prototyping space, a lot of people have been asking me about the ones who are left. One of those is Imperas, which has a combination of technology and models.

On March 3rd, 2008, Imperas made a significant amount of its simulation and virtual prototyping technology public and freely available. This initiative, called Open Virtual Platforms enabled embedded software development to be done on virtual platforms. The technology includes free open source models, documentation on the APIs and a simulator to download. The simulator is free for evaluation and non-commercial usage, but there is now a small charge for usage.

As of January 2010, OVP World has over 2,000 registered users, growing currently at over 150 per month. There are 25+ companies involved to varying degrees, and they have over……

[To read the full article, please visit the blog on TechBites.com here]

SUNNYVALE, Calif. - November 2, 2009 - MIPS Technologies, Inc. (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores, today introduced a new core family providing the highest levels of system performance for extremely cost-sensitive embedded applications such as 32-bit microcontrollers (MCUs), home entertainment, personal entertainment and home networking. The new MIPS32® M14KTM and M14KcTM cores are the first MIPS32-compatible cores that also execute the new microMIPSTM instruction set architecture (ISA), achieving high performance of
1.5 DMIPS/MHz with an advanced level of code compression. The microMIPS ISA maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant …

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Software developers can also take advantage of fast instruction set simulators developed in conjunction with Imperas for use in software development and virtual platforms.
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“We are working together with MIPS to create MIPS-VerifiedTM instruction-accurate models of its newest cores that MIPS will provide to its licensees,” said Simon Davidmann, CEO of Imperas. “With our instruction accurate simulation technology and these models, developers can simulate complete embedded systems running real application code at very fast speeds on typical desktop PCs-helping them get to market quickly at the lowest possible cost.”
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For full text of the release, please read the release on the MIPS site.

by Dick Selwood, IC Design and Verification Journal

Let’s start with some thundering generalisations. It is taking too long to bring SoCs to the market. A big bottleneck, and a large and growing part of the overall cost of an SoC, is developing the software to run on the embedded processors. It is often not possible to begin software development until the chip architecture has been pinned down, which severely limits the influence that the software team can have over the architecture. The desk-top development environment, in which software is usually developed, behaves differently to the target environment. Hardware prototypes in, for example, FPGAs, if they are created, are different again, expensive to create and usually available only late in the development cycle. When the chip becomes available, debugging software running in it can be a nightmare.

This string of problems is only going to get worse as multiple cores, heterogeneous and homogeneous, become the norm for SoCs. If it is not easy to develop software for a single processor, software for multiple processors is recognised as being even more difficult to write and horrendously more difficult to debug.

OK. Common ground so far, and almost every presentation you have sat through covers aspects of this. Why rehearse it again?

Because, if Simon Davidmann and his team at Imperas have got it right, the situation is changing and changing radically.

Simon Davidmann is a very successful serial entrepreneur, with enormous experience in EDA. His web-based CV (Curriculum Vitae or Resume) lists 5 start-ups where he played a significant role. Much of his work has been with some aspect of EDA pioneering, and the list includes names and products like HiLo, SystemVerilog, VCS, and Ambit. His last company, Co-Design Automation, which he co-founded in 1998 and managed as President, CEO and Chairman, was sold to Synopsys for $36 million in mid-2002. He left Synopsys in 2003 and soon after founded Imperas. He (and his team) then spent several years (and, he estimates, about $4 million) developing the basis for a solution of the SoC software problem – a virtual modelling environment for developing software for systems using multiple processors.

Then what did he do?

He only …

[Read the full article at IC Design And Verificaton Journal here]

[To download a pdf click here]

There is now a very good and comprehensive Technical Paper on Virtual Platforms by leading ESL consultant Brian Bailey - this is available to registered users on the main download page under the Whitepapers list.