VinChip offers India-developed 32-bit RISC processor

Peter Clarke, (EETimes)
(06/22/2009 6:42 AM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=218100501

LONDON — VinChip Systems Inc. (San Jose, Calif.) has announced the availability of the VinRZ5110 32-bit RISC processor core, which it claims is the first 32-but processor to be developed in India. It has a DSP-centric instruction set and low gate count for low power consumption, the company said.

VinChip, which has a design center in Chennai, India, said the VinRZ5110 is suitable for use in applications including mass storage, automotive control, wireless devices and audio/video encoders and decoders. It is also suitable for FPGA-based embedded systems.

The core has been developed with on-chip debug logic based on OpenOCD, which also supports in-system programming via JTAG. An optional module, the VinSMDP, provides static and dynamic capture of debug data and in-system programming over USB 2.0 achieving speeds of 480-Mbits per second. The VinSMDP can also multi-task as a USB port for user tasks on the AHB bus.

The VinRZ5110 core has…

[For the full article read here]

[For the VinChip press release go here]

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, has announced its System-Level Catalyst Program to accelerate the adoption of system-level design and verification.

Imperas is a founding charter member, joining at the program’s creation. “The integration of Open Virtual Platforms (OVP) processor models with the Synopsys Innovator tools provides customers with an expanded set of IP with which to build virtual platforms. Moreover, the native TLM-2.0 interface in the instruction accurate OVP models ensures that users will have the fastest possible simulation performance, as is required for software development on virtual platforms, ” said Simon Davidmann, Imperas CEO.

System-Level Catalyst Program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system-level models and services.

The members of the program include Synopsys, Imperas, and many other supporters of the Open Virtual Platforms initiative, including: Carbon, CriticalBlue, Doulos, Forte, GreenSocs, and Tensilica.

[For more information, please see the Synopsys press release here]

Published in issue of Chip Design Magazine

With software development eating up more resources than hardware development, it’s time for a freer and more open approach.

By Duncan Graham and Dhaval Shah

Software is becoming increasingly more important in system design. In fact, software development for embedded systems now requires more resources than hardware development. Software also is becoming increasingly complex, which is leading to problems with bugs, schedules, and code maintenance and updates. This situation is amplified in the case of leading-edge integrated circuits (ICs) or systems-on-a-chip (SoCs) that utilize multiple processor cores. If the SoC is modeled in enough detail, however, the software developers can use the model as a virtual development environment or platform. This approach allows software to be comprehensively tested earlier in the development cycle. The software, which is compiled for the silicon and then run or simulated on a virtual platform, can be more rigorously tested than on the actual hardware. The virtual platform’s observability and controllability also make it easier to debug the code.

This article will illustrate how a virtual platform is constructed and a new Universal Serial Bus (USB) peripheral is created using the specific example of an audio-decode application. The virtual platform utilizes a Tensilica Diamond 570T core. The virtual-platform technology is open source from Open Virtual Platforms (www.OVPworld.org). The example development services were provided by Sibridge Technologies (www.sibridgetech.com).

Figure 1 shows the block diagram for this example. It includes the following features:

• Virtual platform consisting of a Tensilica Diamond 570T core model, USB peripheral model, and memory model running under Windows XP
• Demo application decoding an Ogg Vorbis-compressed audio file and playing the output using USB speakers
• Decompression done on the Tensilica core as a pure C implementation
• A binary-intercept library providing the link between the USB peripheral model and the Windows USB-host peripheral device driver layer

The Tensilica Diamond 570T core model is included in the…

[To read the full article please visit here.]

A Viewpoint by Larry Lapides, Vice President of Sales, Imperas Ltd.

I have a soft spot in my heart for plays and poetry.  I couldn’t have made it through high school English classes without these forms of expression.

Moby Dick?  Have you ever read past “Call me Ishmael?”  There are loads of pages where nothing happens.  Give me e. e. cummings poetry any day.  Or Shakespeare, or Oscar Wilde.  The forms of these genres force playwrights and poets to be concise and precise with their thinking.

Writing poetry is actually a good exercise in that regard, forcing one to focus.  So, let’s apply it to multicore, the topic of the day in the SoC world, just for grins:

Silicon breakthrough:
Multicore SoC, but …
software the issue

Haiku is particularly challenging, with a formal structure of 5-7-5 syllables per line.  But still, you get the point, I hope, as multicore SoCs have been around for a while now.

Software is the issue for these SoCs.  It’s great that fabs keep pushing the silicon technology, enabling more and more functionality on a chip.  Additional processor cores are added continually to the SoCs, but as dedicated resources for specific features.  This isn’t really multicore processing; it’s just multiple processor cores on a chip.

Lest you think that poetry is all seriousness, there’s the limerick:  five lines, inherently humorous due to the vast library of humorous limericks that we’ve read.  (And if you haven’t, I highly recommend Isaac Asimov’s Limericks:  Too Gross as a good place to start.)

There once was a hot semi, fabless,
Thought software the beast from Loch Ness
Turned a great chip,
Multicore, the whole bit
No software? No one bought it, they confess

Back in the real world, semiconductor developers have been building multicore chips for a number of years.  But again, what has been done with them?  One dedicated application per core, which does not take advantage of multicore architecture benefits — namely, higher bandwidth due to more processing power, and lower power consumption due to running processors at lower speeds.

Why haven’t systems been taking advantage of the benefits of multicore?  To paraphrase Shakespeare, from the…

[To read the full article at DACeZine, go here]

Imperas and OVP are participating in a new Virtual Platform Workshop at DAC in July in San Francisco.

WEDNESDAY July 29, 9:00am - 5:30pm | Room 301

Virtual Platforms (VPs) have emerged as a cornerstone in SOC design validation and in embedded software development.  Virtual platforms, a model representation created by assembling component models, enable early software development and lead to fewer silicon re-spins and shorter time-to-market.  This workshop outlines challenges in building and utilizing VPs for software development and verification, and showcases solutions from both vendor and user perspectives.  The purpose of this workshop is to bring together people interested in this topic to promote VPs, educate users about their potential, and to exchange usage experiences.  The intended participants are those interested in various topics associated with VP use and development: IP use, SOC, embedded system, embedded software, and software functional verification.

The workshop begins with a…

[For more information, visit their site...]

We recently noticed that a US based consulting services company - Posedge Software - has put information in the OVP wikki about their OVP services and their work integrating Cadence’s Specman verification tool with OVP Virtual Platforms. To see more information, please visit their page in the OVP wikki.

In early February 2009 we have added OSCI SystemC TLM2.0 support for all the OVP fast models. This allows all OVP models, including the certified processor models, to work in SystemC TLM2.0 platforms. For more information please read the dedicated technology page and visit the dedicated TLM2.0 download page to download the models, examples and standalone demos. Using an OVP CPU model in a TLM2.0 means at last you can run software in your SystemC TLM2.0 platform at 200-500 MIPS. Please download the new OVP installer and read the change logs.

We need to develop tools for those brave enough to develop multicore systems.

A guest column by By Larry Lapides, Imperas Ltd.

In a column a year ago (www.embedded.com/201800330), Bernie Cole compared the state of multicore software tools to the Charge of the Light Brigade: current tools “are as outdated and useless as the sabers, one-shot pistols, and horses of the ill-fated 600 were against cannon, repeating rifles, and mechanized equipment they rode against.”

While it’s not a bad comparison, perhaps a better analogy may be navigating by sea. First, we figured out that the world was round. Then we developed tools to measure longitude to actually figure out where we had come from, where we were, and where we were going. Prior to that, sailors mostly kept within sight of shore or risked getting lost and foundering on some unexpected rocky shore. Those famous sailors, such as Columbus, Magellan, and Cook who successfully navigated large distances over open water, owed their success to luck and pluck more than knowing with certainty where they were and where they were going. And for all the successes we learned about in our history books, there were many more navigational failures.

In addition to death and human suffering due to scurvy, as Dava Sobel points out in her book Longitude, ” the global ignorance of longitude wreaked economic havoc on the grandest scale.” Ships crossing the oceans were confined to a few well-known passages, well known by the pirates and navies in addition to the merchants.

Similarly with multicore, designers have kept close to shore, adding more processing power only to use it for a new, specified application. No sharing of those…

[To read the full article at Embedded.com, please visit here]

In August 2008 we announced a partnership with leading embedded processor IP vendor MIPS Technologies - this includes the availability of MIPS-Verified(tm) core models of the MIPS32 4K, 24K, and multicore 34K processor families. Please see the associated press releases and download and library pages of this web site.

The source of the MIPS processor models is also on the site and this joins the open source of all the released Imperas peripheral models and OpenCores OR1K processor. Please visit the OVP open source Library.

Now released is a MIPS based platform that boots Linux 2.6 - this MIPS Linux platform is perfect for developing applications to run on MIPS Linux - and the hardware virtual platform is just right for porting new versions of Linux or to develop drivers for new hardware. Fast, Free, and Easy to Use - please visit the library/Mips32MaltaLinux page for more information or to download this platform.

To watch a recorded demonstration of how easy it is to download the OVP MIPS Malta Virtual Platform, download and load Linux on it, and then boot Linux to the user prompt in under 5 seconds… then click here to have a look at the videos.