Imperas today announced on the second anniversary of the formation of the Open Virtual Platforms initiative that the new release of its OVPsim reference simulator is now 50% faster than previous versions. This enables embedded software to be developed for ARM, MIPS, ARC, Power Architecture, and NEC processors on simulations running up to 2,000 MIPS on a standard desktop PC.

The new release also comes with new models of Power Architecture processors and also more SystemC TLM 2.0 platforms including a MIPS based Malta platform that boots Linux or Mentor Nucleus.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To find out more about OVP models, virtual platforms and operating system support, please visit the models pages.
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Imperas today announced its relationship with Mentor Graphics Embedded Software Division (ESD) and now makes available virtual platforms for ARM and MIPS processor cores that run the Mentor Nucleus RTOS.

These platforms are free to download and are provided as open source. A binary image of Nucleus 2.2 is provided to demonstrate operation. To download the self contained examples visit the library page on www.OVPworld.org/Nucleus.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To find out more about OVP models, virtual platforms and operating system support, please visit the models pages.
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After much testing the free open source models of the MIPS M14K microMIPS core models are available from the OVP website.

These models of the MIPS32® M14K™ and M14Kc™ processor cores from MIPS Technologies, Inc. include example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools.

MIPS Technologies has verified the functionality of these models under the MIPS-Verified™ program.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To download the MIPS M14K models and platforms and view their source, or to watch videos of MIPS models running at 100s of MIPS, please visit the download pages.

To find out more about OVP models, please visit the models pages.

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After much testing the free open source models of the Virage ARC core models are available from the OVP website.

Models of the Virage Logic ARC® 600 and ARC® 700 families of processor cores have been released, including the ARC® 605.

Virage Logic and Imperas have cooperated on the verification of the functionality of the models.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To download the ARC models and platforms and view their source, or to watch videos of them running at 100s of MIPS, please visit the download pages.

To find out more about OVP models, please visit the models pages.

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After much testing the new free, open source virtual platform and models of the ARM926EJ-S based integrator platform using SystemC TLM2.0 are available from the OVP website.

This relase enables ARM based software to be developed using a free virtual platform which works with OSCI compliant SystemC TLM2.0 simulators.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To download the OVP models of ARM processors and platforms and view their source, or to watch videos of them running at 100s of MIPS, please visit the download pages.

To find out more about OVP models, please visit the models pages.

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After much testing the new free, open source models of the MIPS32 1004K and 74K processors are available from the OVP website.

A press release was released today discussing the availability.

To read the full press release please browse the Press Releases section of this site.

To download the OVP models of MIPS32 processors and view their source, or to watch videos of them running at 100s of MIPS, please visit the download pages.

To find out more about OVP models, please visit the models pages.

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After much testing the new free, open source models of the NEC v850 family of processors are available from the OVP website.

A press release has been released with quotes from users who are benefiting from the significant speed up over their previous solutions.

To read the full press release please browse the Press Releases section of this site.

To download the OVP models of NEC v850 processors and view their source, or to watch videos of them running at 100s of MIPS, please visit the download pages.

To find out more about OVP models, please visit the models pages.

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After much testing the new free, open source models of the ARM7, ARM9, and ARM10 processors are available from the OVP website.

A press release has been released with quotes from two users who are benefiting from the significant speed up over their previous solutions.

The press release also mentions our working with Synopsys with their System-Level Catalyst Program.

To read the full press release please browse the Press Releases section of this site.

To download the OVP models of ARM processors and view their source, or to watch videos of booting Linux, uClinux on them, please visit the download pages.

To find out more about OVP models, please visit the models pages.

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VinChip offers India-developed 32-bit RISC processor

Peter Clarke, (EETimes)
(06/22/2009 6:42 AM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=218100501

LONDON — VinChip Systems Inc. (San Jose, Calif.) has announced the availability of the VinRZ5110 32-bit RISC processor core, which it claims is the first 32-but processor to be developed in India. It has a DSP-centric instruction set and low gate count for low power consumption, the company said.

VinChip, which has a design center in Chennai, India, said the VinRZ5110 is suitable for use in applications including mass storage, automotive control, wireless devices and audio/video encoders and decoders. It is also suitable for FPGA-based embedded systems.

The core has been developed with on-chip debug logic based on OpenOCD, which also supports in-system programming via JTAG. An optional module, the VinSMDP, provides static and dynamic capture of debug data and in-system programming over USB 2.0 achieving speeds of 480-Mbits per second. The VinSMDP can also multi-task as a USB port for user tasks on the AHB bus.

The VinRZ5110 core has…

[For the full article read here]

[For the VinChip press release go here]

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, has announced its System-Level Catalyst Program to accelerate the adoption of system-level design and verification.

Imperas is a founding charter member, joining at the program’s creation. “The integration of Open Virtual Platforms (OVP) processor models with the Synopsys Innovator tools provides customers with an expanded set of IP with which to build virtual platforms. Moreover, the native TLM-2.0 interface in the instruction accurate OVP models ensures that users will have the fastest possible simulation performance, as is required for software development on virtual platforms, ” said Simon Davidmann, Imperas CEO.

System-Level Catalyst Program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system-level models and services.

The members of the program include Synopsys, Imperas, and many other supporters of the Open Virtual Platforms initiative, including: Carbon, CriticalBlue, Doulos, Forte, GreenSocs, and Tensilica.

[For more information, please see the Synopsys press release here]